公开(公告)号：US12154987B2

公开(公告)日：2024-11-26

申请号：US17548827

申请日：2021-12-13

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3115

Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

公开(公告)号：US20220102553A1

公开(公告)日：2022-03-31

申请号：US17548827

申请日：2021-12-13

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

公开(公告)号：US20170365715A1

公开(公告)日：2017-12-21

申请号：US15674266

申请日：2017-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L29/7847 ,  H01L21/31155 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659

Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls, The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.