公开(公告)号：US11616058B2

公开(公告)日：2023-03-28

申请号：US17117421

申请日：2020-12-10

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L27/088 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

公开(公告)号：US11588008B2

公开(公告)日：2023-02-21

申请号：US16800002

申请日：2020-02-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar

IPC: H01L49/02 ,  H01L23/525 ,  H01L27/06 ,  H01L21/8234

Abstract: An integrated circuit includes a polysilicon resistor having a plurality of segments, including first, second and third segments, the second segment located between and running about parallel to the first and third segments. A first header connects the first and second segments, and a second header connects the second and third segments. A first metal silicide layer located over the first header extends over the first and second segments toward the second header. A second metal silicide layer located over the second header extends over the second and third segments toward the first header. A dielectric layer is located over and contacts the first, second and third segments between the first and second metal silicide layers.

公开(公告)号：US20220209012A1

公开(公告)日：2022-06-30

申请号：US17135541

申请日：2020-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Edward Hornung ,  Mahalingam Nandakumar

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/167 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L21/8234

Abstract: An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.

公开(公告)号：US20220208973A1

公开(公告)日：2022-06-30

申请号：US17156612

申请日：2021-01-24

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Alexei Sadovnikov ,  Henry Litzmann Edwards ,  Jarvis Benjamin Jacobs

IPC: H01L29/26 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.

公开(公告)号：US10593680B2

公开(公告)日：2020-03-17

申请号：US15826923

申请日：2017-11-30

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L27/11 ,  H01L27/082 ,  H01L27/092 ,  H01L27/06 ,  H01L29/06 ,  H01L21/266 ,  H01L21/265 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8249 ,  H01L29/732 ,  H01L29/66

Abstract: An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants is blocked from the logic MOS transistors.

公开(公告)号：US10115638B2

公开(公告)日：2018-10-30

申请号：US15174018

申请日：2016-06-06

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/225 ,  H01L21/311 ,  H01L27/11 ,  H01L29/66

Abstract: An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion of the transistors. Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant. Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material and before formation of a replacement gate dielectric layer. Elevating the LDD regions and recessing the replacement gates may increase a channel length of the MOS transistors and thereby desirably increase threshold uniformity of the transistors.

公开(公告)号：US09865599B2

公开(公告)日：2018-01-09

申请号：US14614733

申请日：2015-02-05

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L29/76 ,  H01L29/94 ,  H01L21/8236 ,  H01L29/78 ,  H01L21/336 ,  H01L29/778 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  H01L21/823814 ,  H01L21/823892

Abstract: A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.

公开(公告)号：US09548384B2

公开(公告)日：2017-01-17

申请号：US14282600

申请日：2014-05-20

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Steve Lytle

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit may include a metal gate which extends over an active area and onto an isolation dielectric layer. A conductive spline is formed on the metal gate, extending on the metal gate over at least a portion of the isolation dielectric layer, and extending on the metal gate for a length at least four times a width of the metal gate.

Abstract translation: 集成电路可以包括在有源区上延伸到隔离电介质层上的金属栅极。 导电花键形成在金属栅极上，在金属栅极上延伸至隔离绝缘层的至少一部分上，并在金属栅极上延伸至金属栅极宽度的至少四倍的长度。

公开(公告)号：US20160233312A1

公开(公告)日：2016-08-11

申请号：US15093881

申请日：2016-04-08

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Mahalingam Nandakumar

IPC: H01L29/66 ,  H01L29/51 ,  H01L27/092 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7833

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench

公开(公告)号：US09281304B2

公开(公告)日：2016-03-08

申请号：US13709696

申请日：2012-12-10

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Sunitha Venkataraman ,  David L. Catlett, Jr.

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0274

Abstract: An integrated circuit includes a diode/bipolar ESD protection device. The diode/bipolar ESD device includes at least one gate separated ESD diode and at least one gate spaced ESD bipolar transistor coupled in parallel between a fixed voltage and an input/output pin.

Abstract translation: 集成电路包括二极管/双极ESD保护器件。 二极管/双极ESD器件包括至少一个栅极分离的ESD二极管和至少一个栅极间隔的ESD双极晶体管并联在固定电压和输入/输出引脚之间。