公开(公告)号：US20220165318A1

公开(公告)日：2022-05-26

申请号：US16953602

申请日：2020-11-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mayank GARG ,  Srijan RASTOGI ,  Vivekkumar Ramanlal VADODARIYA ,  Nitesh KEKRE

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/20

Abstract: A serial bus equalization trim circuit includes a first data input terminal, a second data input terminal, a delay circuit, and a flip-flop. The delay circuit includes a data input, a trim input, and an output. The data input is coupled the first data input terminal. The flip-flop includes a data input, a clock input, and an output. The data input is coupled to the output of the delay circuit. The clock input is coupled to the second data input terminal. The output is coupled to the trim input of the delay circuit.