公开(公告)号：US20220165318A1

公开(公告)日：2022-05-26

申请号：US16953602

申请日：2020-11-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mayank GARG ,  Srijan RASTOGI ,  Vivekkumar Ramanlal VADODARIYA ,  Nitesh KEKRE

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/20

Abstract: A serial bus equalization trim circuit includes a first data input terminal, a second data input terminal, a delay circuit, and a flip-flop. The delay circuit includes a data input, a trim input, and an output. The data input is coupled the first data input terminal. The flip-flop includes a data input, a clock input, and an output. The data input is coupled to the output of the delay circuit. The clock input is coupled to the second data input terminal. The output is coupled to the trim input of the delay circuit.

公开(公告)号：US20230318587A1

公开(公告)日：2023-10-05

申请号：US18329805

申请日：2023-06-06

Applicant: Texas Instruments Incorporated

Inventor： Srijan RASTOGI ,  Srikanth MANIAN

IPC: H03K3/037 ,  H03K19/20 ,  H03K5/01

CPC classification number: H03K5/01 ,  H03K3/037 ,  H03K19/20 ,  H03K2005/00019

Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.