公开(公告)号：US20220165318A1

公开(公告)日：2022-05-26

申请号：US16953602

申请日：2020-11-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mayank GARG ,  Srijan RASTOGI ,  Vivekkumar Ramanlal VADODARIYA ,  Nitesh KEKRE

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/20

Abstract: A serial bus equalization trim circuit includes a first data input terminal, a second data input terminal, a delay circuit, and a flip-flop. The delay circuit includes a data input, a trim input, and an output. The data input is coupled the first data input terminal. The flip-flop includes a data input, a clock input, and an output. The data input is coupled to the output of the delay circuit. The clock input is coupled to the second data input terminal. The output is coupled to the trim input of the delay circuit.

公开(公告)号：US20170317619A1

公开(公告)日：2017-11-02

申请号：US15142852

申请日：2016-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shyamsunder BALASUBRAMANIAN ,  Toshio YAMANAKA ,  Toru TANAKA ,  Mayank GARG

IPC: H02P6/12 ,  H03K17/687

Abstract: A gate driver circuit includes a comparator and a gate driver. The comparator is configured to detect a short circuit in a first power field effect transistor (FET). The gate driver is configured to drive a gate of the first power FET by generating a first signal at a first drive current. In response to the comparator detecting a short circuit in the first power FET, the gate driver is further configured to pulse the first signal at a first pulldown current. After the pulse has ended, the gate driver is further configured to drive the gate of the first power FET at a first hold current. The first hold current is less than the first pulldown current.

公开(公告)号：US20220391345A1

公开(公告)日：2022-12-08

申请号：US17341089

申请日：2021-06-07

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar KAMATH ,  Rakesh HARIHARAN ,  Vivekkumar Ramanlal VADODARIYA ,  Soumi PAUL ,  Mayank GARG

IPC: G06F13/42 ,  G06F13/38 ,  G06F1/3215

Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.

公开(公告)号：US20170317638A1

公开(公告)日：2017-11-02

申请号：US15143030

申请日：2016-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Toshio YAMANAKA ,  Shyamsunder BALASUBRAMANIAN ,  Toru TANAKA ,  Mayank GARG

IPC: H02P31/00 ,  H02H7/09 ,  H02H7/08

CPC classification number: H02P31/00 ,  B60L3/00 ,  G06F1/28 ,  H02H7/0844 ,  H02H7/09

Abstract: An apparatus includes a control circuit that includes a configuration register and configured to receive a configuration setting across an external bus. The configuration setting encodes a first voltage state for the apparatus. The control circuit includes an input configured to be coupled to an external electrical device. The control circuit is configured to determine a value of the external device that maps to a second voltage state for the apparatus. The control logic is configured to transition the apparatus to a safe mode upon a determination that the first voltage state does not match the second voltage state.

公开(公告)号：US20170288622A1

公开(公告)日：2017-10-05

申请号：US15142134

申请日：2016-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wenxiao TAN ,  Mayank GARG ,  Noble NARKU-TETTEH

IPC: H03F3/45 ,  H02P31/00 ,  G11C7/06 ,  H03F1/56

CPC classification number: H03F3/45677 ,  G11C7/06 ,  G11C29/028 ,  G11C29/50008 ,  G11C2029/0407 ,  H02P31/00 ,  H03F1/56 ,  H03F3/45179 ,  H03F2200/481 ,  H03F2203/45306

Abstract: An electrical device (e.g., an integrated circuit) includes an amplifier, a configurable common mode gain trim circuit, and a memory. The configurable common mode gain trim circuit is coupled to the amplifier. The memory is configured to include trim data that is usable during an initialization process for the electrical device to configure the impedance matching circuit.

公开(公告)号：US20230004516A1

公开(公告)日：2023-01-05

申请号：US17363106

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Ganapathi HEGDE ,  Krushal SHAH ,  Mayank GARG ,  Luis Eduardo OSSA ,  Vashist BIST

IPC: G06F13/42

Abstract: A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.

公开(公告)号：US20210328536A1

公开(公告)日：2021-10-21

申请号：US16849680

申请日：2020-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krushal SHAH ,  Mayank GARG ,  Ganapathi HEGDE

IPC: H02P27/08 ,  H02M7/5387 ,  H02P6/28

Abstract: A system includes a motor and a motor controller coupled to the motor. The motor controller includes a current sense circuit configured to: receive a first phase current sense measurement on a first measurement path; receive the first phase current sense measurement on a second measurement path; receive a second phase current measurement on the first measurement path; receive the second phase current on the second measurement path; average the first phase current sense measurement on the first measurement path with the first phase current sense measurement on the second path; and average the second phase current sense measurement on the first measurement path with the second phase current sense measurement on the second path.

公开(公告)号：US20190296695A1

公开(公告)日：2019-09-26

申请号：US15934467

申请日：2018-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shyamsunder BALASUBRAMANIAN ,  Wenxiao TAN ,  Mayank GARG ,  Toru TANAKA

IPC: H03F1/30 ,  H03F3/04

Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.