Multi-phase clock generation circuit

    公开(公告)号:US10659059B2

    公开(公告)日:2020-05-19

    申请号:US16454982

    申请日:2019-06-27

    Abstract: A multi-phase clock circuit includes a first delay circuit, a second delay circuit, a third delay circuit, a first clock mixer circuit, and a second clock mixer circuit. The first, second, and third delay circuits are coupled in series. The first clock mixer circuit includes a first input and a second input. The first input is coupled to an output of the first delay circuit. The second input is coupled to an output of the second delay circuit. The second clock mixer circuit also includes a first input and a second input. The first input of the second clock mixer circuit is coupled to an output of the second delay circuit. The second input of the second clock mixer circuit is coupled to an output of the third delay circuit.

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