公开(公告)号：US20140266361A1

公开(公告)日：2014-09-18

申请号：US13886637

申请日：2013-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siddharth Shashidharan ,  Sumantra Seth ,  Ravi Jithendra Mehta ,  Biman Chattopadhyay ,  Sujoy Chinmoy Chakravarty

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: In an embodiment, a duty cycle correction circuit comprises a first set of inverters connected in series, a first filter, a first feedback circuit and a second feedback circuit. A first inverter in the series is configured to receive a clock signal and a last inverter in the series is configured to provide a first output clock signal. The first filter is configured to generate a first direct current (DC) voltage signal at an output of the first filter. The first feedback circuit is configured to control a rise time of a signal transition at an output terminal of the first inverter to control a duty cycle of the first output clock cycle. The second feedback circuit is configured to control a fall time of the signal transition at the output terminal of the first inverter to control the duty cycle of the first output clock cycle.

Abstract translation: 在一个实施例中，占空比校正电路包括串联连接的第一组反相器，第一滤波器，第一反馈电路和第二反馈电路。 串联的第一反相器被配置为接收时钟信号，并且串联中的最后一个反相器被配置为提供第一输出时钟信号。 第一滤波器被配置为在第一滤波器的输出处产生第一直流（DC）电压信号。 第一反馈电路被配置为控制第一反相器的输出端处的信号转变的上升时间，以控制第一输出时钟周期的占空比。 第二反馈电路被配置为控制第一反相器的输出端处的信号转变的下降时间，以控制第一输出时钟周期的占空比。