公开(公告)号：US20140247071A1

公开(公告)日：2014-09-04

申请号：US14258771

申请日：2014-04-22

Applicant: Texas Instruments Incorporated

Inventor： Sumantra Seth ,  Somasunder Kattepura Sreenath ,  Sujoy Chinmoy Chakravarty ,  Arakali Abhijith

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G06F1/26 ,  H02J2007/0062 ,  H03K19/0185

Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.

Abstract translation: 用于确保USB-OTG（On Go Go）会话请求协议的Ultra Deep Sub Micron（UDSM）过程中的VBUS脉冲的架构，该体系结构是至少部署充电电路的类型，其使用连接在 充电电路的前进路径。 该架构可以包括二极管分压器，其包括节点并且在所述充电电路中从VBUS连接。 一个实施例使用包括晶体管的充电和放电电路。 充电电路晶体管可以包括PMOS晶体管，并且放电电路晶体管可以包括NMOS晶体管。 该结构可以包括连接在所述VBUS和地之间的接近100K欧姆的总电阻值的三个电阻串，其中放电电路晶体管可以包括漏极延伸的NMOS晶体管。 充电和放电电路晶体管具有约3.6V的VDS和VGD，由此不需要高VGS晶体管。

公开(公告)号：US20140266361A1

公开(公告)日：2014-09-18

申请号：US13886637

申请日：2013-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siddharth Shashidharan ,  Sumantra Seth ,  Ravi Jithendra Mehta ,  Biman Chattopadhyay ,  Sujoy Chinmoy Chakravarty

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: In an embodiment, a duty cycle correction circuit comprises a first set of inverters connected in series, a first filter, a first feedback circuit and a second feedback circuit. A first inverter in the series is configured to receive a clock signal and a last inverter in the series is configured to provide a first output clock signal. The first filter is configured to generate a first direct current (DC) voltage signal at an output of the first filter. The first feedback circuit is configured to control a rise time of a signal transition at an output terminal of the first inverter to control a duty cycle of the first output clock cycle. The second feedback circuit is configured to control a fall time of the signal transition at the output terminal of the first inverter to control the duty cycle of the first output clock cycle.

Abstract translation: 在一个实施例中，占空比校正电路包括串联连接的第一组反相器，第一滤波器，第一反馈电路和第二反馈电路。 串联的第一反相器被配置为接收时钟信号，并且串联中的最后一个反相器被配置为提供第一输出时钟信号。 第一滤波器被配置为在第一滤波器的输出处产生第一直流（DC）电压信号。 第一反馈电路被配置为控制第一反相器的输出端处的信号转变的上升时间，以控制第一输出时钟周期的占空比。 第二反馈电路被配置为控制第一反相器的输出端处的信号转变的下降时间，以控制第一输出时钟周期的占空比。

公开(公告)号：US09065430B2

公开(公告)日：2015-06-23

申请号：US14258771

申请日：2014-04-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sumantra Seth ,  Somasunder Kattepura Sreenath ,  Sujoy Chinmoy Chakravarty ,  Arakali Abhijith

IPC: H03K19/094 ,  G06F13/20 ,  H03K3/012 ,  G06F1/26 ,  H03K19/0185 ,  H02J7/00

CPC classification number: H03K3/012 ,  G06F1/26 ,  H02J2007/0062 ,  H03K19/0185

Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.

Abstract translation: 用于确保USB-OTG（On Go Go）会话请求协议的Ultra Deep Sub Micron（UDSM）过程中的VBUS脉冲的架构，该体系结构是至少部署充电电路的类型，其使用连接在 充电电路的前进路径。 该架构可以包括二极管分压器，其包括节点并且在所述充电电路中从VBUS连接。 一个实施例使用包括晶体管的充电和放电电路。 充电电路晶体管可以包括PMOS晶体管，并且放电电路晶体管可以包括NMOS晶体管。 该结构可以包括连接在所述VBUS和地之间的接近100K欧姆的总电阻值的三个电阻串，其中放电电路晶体管可以包括漏极延伸的NMOS晶体管。 充电和放电电路晶体管具有约3.6V的VDS和VGD，由此不需要高VGS晶体管。