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1.发明授权公开(公告)号：US12136918B2
公开(公告)日：2024-11-05
申请号：US17872841
申请日：2022-07-25
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Sumantra Seth , Baher Haroun
Abstract: A driver system includes a non-inverting system input, an inverting system input, a non-inverting system output and an inverting system output. The driver system includes a line driver which includes a non-inverting driver input coupled to the non-inverting system input and includes an inverting driver input coupled to the inverting system input. The line driver includes an inverting driver output and a non-inverting driver output. The driver system includes a first termination resistor coupled between the non-inverting driver output and the non-inverting system output and includes a second termination resistor coupled between the inverting driver output and the inverting system output. The driver system includes a first amplifier stage coupled to the line driver and includes a second amplifier stage coupled to the line driver.
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公开(公告)号：US11615040B2
公开(公告)日：2023-03-28
申请号：US17390428
申请日：2021-07-30
Applicant: Texas Instruments Incorporated
Inventor： Geet Govind Modi , Sumantra Seth , Subhashish Mukherjee
Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.
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公开(公告)号：US20230035848A1
公开(公告)日：2023-02-02
申请号：US17390428
申请日：2021-07-30
Applicant: Texas Instruments Incorporated
Inventor： Geet Govind Modi , Sumantra Seth , Subhashish Mukherjee
Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.
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4.发明授权公开(公告)号：US09496007B2
公开(公告)日：2016-11-15
申请号：US14503545
申请日：2014-10-01
Applicant: Texas Instruments Incorporated
Inventor： Sumantra Seth , Subrato Roy , Deepak Verma
Abstract: The disclosure provides a voltage regulator for generating piece-wise linear regulated supply voltage. The voltage regulator includes a first clamp circuit that receives a reference voltage and an analog supply voltage. A second clamp circuit receives the reference voltage. A voltage divider circuit is coupled to the first clamp circuit and the second clamp circuit. The voltage divider circuit receives a peripheral supply voltage and generates a regulated supply voltage.
Abstract translation: 本公开提供了用于产生分段线性稳压电源电压的电压调节器。 电压调节器包括接收参考电压和模拟电源电压的第一钳位电路。 第二钳位电路接收参考电压。 分压器电路耦合到第一钳位电路和第二钳位电路。 分压器电路接收外围电源电压并产生稳定的电源电压。
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公开(公告)号：US20140247071A1
公开(公告)日：2014-09-04
申请号：US14258771
申请日：2014-04-22
Applicant: Texas Instruments Incorporated
Inventor： Sumantra Seth , Somasunder Kattepura Sreenath , Sujoy Chinmoy Chakravarty , Arakali Abhijith
IPC: H03K3/012
CPC classification number: H03K3/012 , G06F1/26 , H02J2007/0062 , H03K19/0185
Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.
Abstract translation: 用于确保USB-OTG（On Go Go）会话请求协议的Ultra Deep Sub Micron（UDSM）过程中的VBUS脉冲的架构，该体系结构是至少部署充电电路的类型，其使用连接在 充电电路的前进路径。 该架构可以包括二极管分压器，其包括节点并且在所述充电电路中从VBUS连接。 一个实施例使用包括晶体管的充电和放电电路。 充电电路晶体管可以包括PMOS晶体管，并且放电电路晶体管可以包括NMOS晶体管。 该结构可以包括连接在所述VBUS和地之间的接近100K欧姆的总电阻值的三个电阻串，其中放电电路晶体管可以包括漏极延伸的NMOS晶体管。 充电和放电电路晶体管具有约3.6V的VDS和VGD，由此不需要高VGS晶体管。
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Patent Agency Ranking
6.发明公开公开(公告)号：US20240030900A1
公开(公告)日：2024-01-25
申请号：US17872841
申请日：2022-07-25
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Sumantra Seth , Baher Haroun
CPC classification number: H03K3/01 , H03F3/45475
Abstract: A driver system includes a non-inverting system input, an inverting system input, a non-inverting system output and an inverting system output. The driver system includes a line driver which includes a non-inverting driver input coupled to the non-inverting system input and includes an inverting driver input coupled to the inverting system input. The line driver includes an inverting driver output and a non-inverting driver output. The driver system includes a first termination resistor coupled between the non-inverting driver output and the non-inverting system output and includes a second termination resistor coupled between the inverting driver output and the inverting system output. The driver system includes a first amplifier stage coupled to the line driver and includes a second amplifier stage coupled to the line driver.
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公开(公告)号：US11171603B2
公开(公告)日：2021-11-09
申请号：US17074688
申请日：2020-10-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumantra Seth , Isha Khandelwal , Rama Santosh Neelim Kumar Kattamuri
Abstract: An integrated circuit includes an inverter, first and second capacitors, a resistor, and a transistor. The inverter has an input and an output. The first capacitor is coupled to a ground. The transistor has a first transistor terminal, a second transistor terminal, and a control input. The first transistor terminal is coupled to the first capacitor and the second transistor terminal is coupled to the input of the inverter. The second capacitor is coupled between the output of the inverter and the ground. The resistor is coupled between the output of the inverter and the first transistor terminal.
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公开(公告)号：US20140266361A1
公开(公告)日：2014-09-18
申请号：US13886637
申请日：2013-05-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Siddharth Shashidharan , Sumantra Seth , Ravi Jithendra Mehta , Biman Chattopadhyay , Sujoy Chinmoy Chakravarty
IPC: H03K3/017
CPC classification number: H03K5/1565
Abstract: In an embodiment, a duty cycle correction circuit comprises a first set of inverters connected in series, a first filter, a first feedback circuit and a second feedback circuit. A first inverter in the series is configured to receive a clock signal and a last inverter in the series is configured to provide a first output clock signal. The first filter is configured to generate a first direct current (DC) voltage signal at an output of the first filter. The first feedback circuit is configured to control a rise time of a signal transition at an output terminal of the first inverter to control a duty cycle of the first output clock cycle. The second feedback circuit is configured to control a fall time of the signal transition at the output terminal of the first inverter to control the duty cycle of the first output clock cycle.
Abstract translation: 在一个实施例中，占空比校正电路包括串联连接的第一组反相器，第一滤波器，第一反馈电路和第二反馈电路。 串联的第一反相器被配置为接收时钟信号，并且串联中的最后一个反相器被配置为提供第一输出时钟信号。 第一滤波器被配置为在第一滤波器的输出处产生第一直流（DC）电压信号。 第一反馈电路被配置为控制第一反相器的输出端处的信号转变的上升时间，以控制第一输出时钟周期的占空比。 第二反馈电路被配置为控制第一反相器的输出端处的信号转变的下降时间，以控制第一输出时钟周期的占空比。
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公开(公告)号：US20240136977A1
公开(公告)日：2024-04-25
申请号：US17972532
申请日：2022-10-23
Applicant: Texas Instruments Incorporated
Inventor： Srikanth Manian , Sumantra Seth , Trilok Kamagond
CPC classification number: H03F1/02 , H03F3/45475 , H03F2200/129
Abstract: A driver includes an operational amplifier which includes a first amplifier input coupled to a first driver input, a second amplifier input coupled to a second driver input, a first amplifier output, a second amplifier output, a third amplifier output and a fourth amplifier output. The first amplifier output is coupled to the first driver output and the third amplifier output is coupled to the second driver output in a voltage-mode operation. The second amplifier output is coupled to the first driver output and the fourth amplifier output is coupled to the second driver output in a current-mode operation.
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公开(公告)号：US20230229607A1
公开(公告)日：2023-07-20
申请号：US18126602
申请日：2023-03-27
Applicant: Texas Instruments Incorporated
Inventor： Geet Govind Modi , Sumantra Seth , Subhashish Mukherjee
Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.
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