DYNAMIC PULSE WIDTH CONTROL SCHEME IN AMPLIFIERS

    公开(公告)号:US20240213935A1

    公开(公告)日:2024-06-27

    申请号:US18088091

    申请日:2022-12-23

    CPC classification number: H03F3/2173 H03F1/3205 H03F2200/03 H03F2200/351

    Abstract: Examples of amplifiers and components thereof are configured to adjust the OFF-pulse widths of a high-duty cycle pulse width modulated (PWM) output signal and the ON-pulse widths of a low-duty cycle PWM output signal. Such control is carried out using high- and low-side (HS and LS) detectors. The HS detector coupled to the control terminal of an HS transistor detects when the gate-to-source voltage (Vgs) of the HS transistor drops below a threshold and outputs an HS detection signal to adjust the OFF-pulse widths of the high-duty cycle PWM output signal. An LS detector coupled to the control terminal of an LS transistor detects when the Vgs of the LS transistor drops below the threshold and outputs a LS detection signal to adjust the ON-pulse widths of the low-duty cycle PWM output signal.

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