Slope compensation induced offset error cancellation in a peak or valley current mode switching voltage regulator

    公开(公告)号:US12176812B2

    公开(公告)日:2024-12-24

    申请号:US17875192

    申请日:2022-07-27

    Abstract: A converter includes an inductor and a transistor. A sense circuit couples to the transistor. The sense circuit generates a sense signal responsive to a current through the first transistor. A comparator has first and second comparator inputs and a comparator output. The comparator output controls a signal to the transistor's control input. An error amplifier has an error amplifier input and an error amplifier output coupled to the first comparator input. A slope compensation circuit couples to at least one of the error amplifier output or the sense circuit and generates a slope signal. A peak detection sample/hold (PK-S/H) tracks the slope signal and, responsive to the transistor being turned off, samples the slope signal and provides the sampled slope signal on its output. The PK-S/H output couples to whichever of the error amplifier or sense circuit to which the slope compensation circuit is not coupled.

    FIXED-FREQUENCY HYSTERETIC DC-DC CONVERTER
    2.
    发明公开

    公开(公告)号:US20230188037A1

    公开(公告)日:2023-06-15

    申请号:US18065972

    申请日:2022-12-14

    CPC classification number: H02M3/158 H02M1/088

    Abstract: In described example, a circuit includes an error amplifier that receives a reference voltage and an output voltage, and generates an error signal. A comparator receives the error signal and a feedback signal, and generates a primary signal. A logic circuit is coupled to an output terminal of the comparator, and receives a clocking pulse. A clocking circuit is coupled to one of a first and a second output terminal of the logic circuit. The clocking circuit receives a clock signal and generates the clocking pulse. A driver circuit is coupled to the logic circuit. A switching circuit, coupled to the driver circuit, receives an input voltage and generates a switching voltage at a switching node. The switching circuit having a first switch coupled to a second switch at the switching node.

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