公开(公告)号：US20240313768A1

公开(公告)日：2024-09-19

申请号：US18306378

申请日：2023-04-25

Applicant: Texas Instruments Incorporated

Inventor： Sri Navaneethakrishnan Easwaran ,  Angelo Pereira ,  Yueming Sun ,  Kae Wong ,  Ahmed E Hashim ,  Artur Lewinski

IPC: H03K17/687 ,  H03K17/10 ,  H03K17/567

CPC classification number: H03K17/687 ,  H01L27/02 ,  H03K17/102 ,  H03K17/567

Abstract: Described embodiments include a voltage converter power circuit having a high-voltage rated first transistor with a first current terminal coupled to an input voltage terminal, and a second current terminal. A second transistor, a low-voltage rated transistor, has a second control terminal, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to a switching terminal. A third transistor, a high-voltage rated transistor, has a fifth current terminal coupled to the switching terminal, a sixth current terminal, and a third control terminal. A fourth transistor, a low-voltage rated transistor, is coupled between the sixth current terminal and a ground terminal. A bleeder circuit is coupled between the seventh and eighth current terminals and is configured to prevent a voltage across the fourth transistor from exceeding a breakdown voltage.

公开(公告)号：US10821922B2

公开(公告)日：2020-11-03

申请号：US15212535

申请日：2016-07-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： George Konnail ,  Angelo Pereira ,  Hasibur Rahman ,  Xiaochun Zhao ,  Artur Juliusz Lewinski

IPC: G06F1/32 ,  B60R16/03 ,  G06F1/3203 ,  G06F1/3287

Abstract: One example includes a power control system. The power control system includes an activation controller that is powered via a first power voltage generated via a first power supply and is configured to provide an enable signal. The activation controller can assert the enable signal in response to an input activation signal to control activation of a second power supply. The second power supply can generate a second power voltage in response to the enable signal being asserted. The second power voltage can be provided to regulate power associated with ancillary electronic circuitry. The system also includes a deactivation controller that is powered via the second power voltage and is configured to generate a disable signal to de-assert the enable signal in response to one of a plurality of predetermined deactivation conditions.

公开(公告)号：US20230188037A1

公开(公告)日：2023-06-15

申请号：US18065972

申请日：2022-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Antonio Priego ,  Gerhard Thiele ,  Johann-Erich Bayer ,  Mitsuyori Saito ,  Rida Assaad ,  Angelo Pereira

IPC: H02M3/158 ,  H02M1/088

CPC classification number: H02M3/158 ,  H02M1/088

Abstract: In described example, a circuit includes an error amplifier that receives a reference voltage and an output voltage, and generates an error signal. A comparator receives the error signal and a feedback signal, and generates a primary signal. A logic circuit is coupled to an output terminal of the comparator, and receives a clocking pulse. A clocking circuit is coupled to one of a first and a second output terminal of the logic circuit. The clocking circuit receives a clock signal and generates the clocking pulse. A driver circuit is coupled to the logic circuit. A switching circuit, coupled to the driver circuit, receives an input voltage and generates a switching voltage at a switching node. The switching circuit having a first switch coupled to a second switch at the switching node.

公开(公告)号：US10581416B2

公开(公告)日：2020-03-03

申请号：US16361154

申请日：2019-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Junhong Zhang ,  Angelo Pereira ,  Pinar Korkmaz ,  Sujan Manohar ,  Michael Munroe

IPC: H03K4/06 ,  H03L7/00 ,  H02M3/158 ,  H03K5/135 ,  G06F1/12 ,  H03K3/027

Abstract: Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.