公开(公告)号：US12176812B2

公开(公告)日：2024-12-24

申请号：US17875192

申请日：2022-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kae Wong ,  Rida Assaad

IPC: H02M3/158 ,  H02M1/00

Abstract: A converter includes an inductor and a transistor. A sense circuit couples to the transistor. The sense circuit generates a sense signal responsive to a current through the first transistor. A comparator has first and second comparator inputs and a comparator output. The comparator output controls a signal to the transistor's control input. An error amplifier has an error amplifier input and an error amplifier output coupled to the first comparator input. A slope compensation circuit couples to at least one of the error amplifier output or the sense circuit and generates a slope signal. A peak detection sample/hold (PK-S/H) tracks the slope signal and, responsive to the transistor being turned off, samples the slope signal and provides the sampled slope signal on its output. The PK-S/H output couples to whichever of the error amplifier or sense circuit to which the slope compensation circuit is not coupled.

公开(公告)号：US20240313768A1

公开(公告)日：2024-09-19

申请号：US18306378

申请日：2023-04-25

Applicant: Texas Instruments Incorporated

Inventor： Sri Navaneethakrishnan Easwaran ,  Angelo Pereira ,  Yueming Sun ,  Kae Wong ,  Ahmed E Hashim ,  Artur Lewinski

IPC: H03K17/687 ,  H03K17/10 ,  H03K17/567

CPC classification number: H03K17/687 ,  H01L27/02 ,  H03K17/102 ,  H03K17/567

Abstract: Described embodiments include a voltage converter power circuit having a high-voltage rated first transistor with a first current terminal coupled to an input voltage terminal, and a second current terminal. A second transistor, a low-voltage rated transistor, has a second control terminal, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to a switching terminal. A third transistor, a high-voltage rated transistor, has a fifth current terminal coupled to the switching terminal, a sixth current terminal, and a third control terminal. A fourth transistor, a low-voltage rated transistor, is coupled between the sixth current terminal and a ground terminal. A bleeder circuit is coupled between the seventh and eighth current terminals and is configured to prevent a voltage across the fourth transistor from exceeding a breakdown voltage.