公开(公告)号：US11119909B2

公开(公告)日：2021-09-14

申请号：US16590515

申请日：2019-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland Beaudoin ,  Ritesh Dhirajlal Sojitra ,  Samuel Paul Visalli

IPC: G11C29/00 ,  G06F12/02 ,  G06F12/0879 ,  G11C11/409 ,  G11C29/42 ,  G06F13/40

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

公开(公告)号：US12204443B2

公开(公告)日：2025-01-21

申请号：US18449025

申请日：2023-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland Beaudoin ,  Ritesh Dhirajlal Sojitra ,  Samuel Paul Visalli

IPC: G06F12/02 ,  G06F12/0879 ,  G06F13/40 ,  G11C11/409 ,  G11C29/00 ,  G11C29/42

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

公开(公告)号：US11726907B2

公开(公告)日：2023-08-15

申请号：US17474141

申请日：2021-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland Beaudoin ,  Ritesh Dhirajlal Sojitra ,  Samuel Paul Visalli

IPC: G11C29/00 ,  G06F12/02 ,  G06F12/0879 ,  G11C11/409 ,  G11C29/42 ,  G06F13/40

CPC classification number: G06F12/0246 ,  G06F12/0292 ,  G06F12/0879 ,  G06F13/4027 ,  G11C11/409 ,  G11C29/42 ,  G11C29/76

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.