公开(公告)号：US20220131551A1

公开(公告)日：2022-04-28

申请号：US17570658

申请日：2022-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy NURANI ,  Joseph Palackal MATHEW ,  Prasanth K. ,  Visvesvaraya Appala PENTAKOTA ,  Shagun DUSAD

IPC: H03M1/12 ,  G11C27/02

Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.

公开(公告)号：US20220271764A1

公开(公告)日：2022-08-25

申请号：US17182339

申请日：2021-02-23

Applicant: Texas Instruments Incorporated

Inventor： Prasanth K ,  Eeshan MIGLANI ,  Visvesvaraya Appala PENTAKOTA ,  Kartik GOEL ,  Jagannathan VENKATARAMAN ,  Sai Aditya Krishnaswamy NURANI

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/00 ,  H03K5/24

Abstract: A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described.

公开(公告)号：US20210328595A1

公开(公告)日：2021-10-21

申请号：US16850597

申请日：2020-04-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy NURANI ,  Joseph Palackal MATHEW ,  Prasanth K ,  Visvesvaraya Appala PENTAKOTA ,  Shagun DUSAD

IPC: H03M1/12 ,  G11C27/02

Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.