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    CONVERSION AND FOLDING CIRCUIT FOR DELAY-BASED ANALOG-TO-DIGITAL CONVERTER SYSTEM
    1.
    发明申请
    CONVERSION AND FOLDING CIRCUIT FOR DELAY-BASED ANALOG-TO-DIGITAL CONVERTER SYSTEM 审中-公开

    公开(公告)号：US20200259502A1

    公开(公告)日：2020-08-13

    申请号：US16860334

    申请日：2020-04-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shagun DUSAD ,  Chirag Chandrahas SHETTY ,  Visvesvaraya Appala PENTAKOTA

    IPC: H03M1/50 ,  H03M1/14 ,  H03M1/20 ,  H03M1/44

    Abstract: An RF receiver including: an antenna cable of receiving an RF signal; a low noise amplifier coupled to the antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit having: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals; and

    DELAY-BASED RESIDUE STAGE
    3.
    发明申请
    DELAY-BASED RESIDUE STAGE 审中-公开

    公开(公告)号：US20200259501A1

    公开(公告)日：2020-08-13

    申请号：US16860145

    申请日：2020-04-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Visvesvaraya Appala PENTAKOTA ,  Rishi SOUNDARARAJAN ,  Shagun DUSAD ,  Chirag Chandrahas SHETTY

    IPC: H03M1/38 ,  H03K5/24

    Abstract: An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input. The analog-to-digital converter further includes a digital block having an input connected to the sign signal output of the delay comparator.

    Bias Removal in PRBS Based Channel Estimation
    6.
    发明申请
    Bias Removal in PRBS Based Channel Estimation 审中-公开

    公开(公告)号：US20180351667A1

    公开(公告)日：2018-12-06

    申请号：US16058007

    申请日：2018-08-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shagun DUSAD ,  Nagarajan VISWANATHAN

    IPC: H04B17/336 ,  H04L1/24 ,  H04B17/309 ,  H04L25/02

    CPC classification number: H04B17/336 ,  H04B17/309 ,  H04L1/244 ,  H04L25/0202 ,  H04L25/0226

    Abstract: A system includes a pseudorandom binary sequence (PRBS) generator configured to generate a first PRBS and a second PRBS and an exclusive-OR logic configured to exclusive-OR the first PRBS and the second PRBS to compute a third PRBS. The system also includes an adder, a correlator and a corrector. The adder adds the third PRBS to input data to compute summed data for transmission of the summed data across the channel. The correlator computes the exclusive-OR of the first PRBS and the second PRBS to reproduce the third PRBS and correlates output data from the channel to the reproduced third PRBS to compute a channel gain error and a channel memory error. The corrector extracts the input data from the output data from the channel using the computed channel gain and memory errors.

    Counter-Based SYSREF Implementation
    7.
    发明申请
    Counter-Based SYSREF Implementation 审中-公开

    公开(公告)号：US20180323790A1

    公开(公告)日：2018-11-08

    申请号：US16036221

    申请日：2018-07-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shagun DUSAD ,  Visvesvaraya PENTAKOTA ,  Mark Baxter WEAVER ,  William BRIGHT ,  Jiankun HU

    IPC: H03L7/08

    CPC classification number: H03L7/08 ,  G06F1/12 ,  H03L7/16

    Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.

    CALIBRATION TECHNIQUE FOR CURRENT STEERING DAC
    8.
    发明申请
    CALIBRATION TECHNIQUE FOR CURRENT STEERING DAC 有权
    电流转向DAC的校准技术

    公开(公告)号：US20170041014A1

    公开(公告)日：2017-02-09

    申请号：US15048027

    申请日：2016-02-19

    Applicant: Texas Instruments Incorporated

    Inventor： Neeraj SHRIVASTAVA ,  Supreet JOSHI ,  Himanshu VARSHNEY ,  Jafar Sadique KAVILADATH ,  Visvesvaraya PENTAKOTA ,  Shagun DUSAD

    IPC: H03M1/10 ,  H03M1/74 ,  H03M1/78

    CPC classification number: H03M1/1009 ,  H03M1/1019 ,  H03M1/1057 ,  H03M1/66 ,  H03M1/742 ,  H03M1/745 ,  H03M1/785

    Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

    Abstract translation: 本公开提供了包括多个DAC元件的电流转向数模转换器（DAC）。 多个DAC元件中的至少一个DAC元件耦合到校准电路。 校准电路包括通过第一估计开关耦合到DAC元件的主节点的固定电流源。 数字码发生器耦合到主节点，并且产生对应于在主节点处产生的主电压的第一数字码。 数字代码生成器产生第二数字代码。 校正DAC耦合到数字代码发生器并且基于第二数字代码产生偏置电压。 偏置电压被提供给DAC元件，使得流过多个DAC元件中的每个DAC元件的电流相等。

    CLOCK FILTER WITH NEGATIVE RESISTOR CIRCUIT
    9.
    发明申请
    CLOCK FILTER WITH NEGATIVE RESISTOR CIRCUIT 有权

    公开(公告)号：US20210399720A1

    公开(公告)日：2021-12-23

    申请号：US17463588

    申请日：2021-09-01

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Eeshan MIGLANI ,  Shagun DUSAD

    IPC: H03H11/12 ,  G06F1/10 ,  H03K19/20

    Abstract: A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter. The filter includes a notch filter and a bandpass filter.

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