公开(公告)号：US20250147672A1

公开(公告)日：2025-05-08

申请号：US18591959

申请日：2024-02-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Y.A. ,  Sriramakrishnan Govindarajan ,  Mohd Asif Farooqui ,  Shailesh Ganapat Ghotgalkar ,  Sai Karthik Rajaraman ,  Pratheesh Gangadhar TK ,  David Smith ,  Niraj Nandan

IPC: G06F3/06

Abstract: Systems and methods for servicing read requests may include receiving a transaction from a processing unit while mirroring contents from an external memory to an on-chip RAM. Such systems and methods may monitor a progress of the mirroring and, based on the monitoring, access code or data values for the transaction from either the external memory or the on-chip RAM. Such systems and methods may further provide the code or data values to the processing unit according to the transaction. Such systems and methods may allow for execution of software before software has been fully downloaded to internal memory.

公开(公告)号：US20250156354A1

公开(公告)日：2025-05-15

申请号：US18933348

申请日：2024-10-31

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Sriramakrishnan Arumbuliyur Govindarajan ,  Sai Karthik Rajaraman ,  Pratheesh Gangadhar Thalakkal Kottila Veedu ,  Niraj Nandan ,  Mel Alan Phipps

IPC: G06F13/28

Abstract: An example accelerator circuit includes a direct memory access (DMA) circuit configured to copy contents of an off-chip memory to an internal memory of a device. In some examples, the off-chip memory is external to the device. The example accelerator circuit also includes a decoder circuit configured to determine a transaction from a processor circuit of the device is associated with a memory address included in a region of the off-chip memory to be copied to the internal memory. In some examples, the decoder circuit is also configured to direct the transaction to one of the off-chip memory or the internal memory based on whether a DMA copy of the region of the off-chip memory to the internal memory has completed.

公开(公告)号：US20250147752A1

公开(公告)日：2025-05-08

申请号：US18659615

申请日：2024-05-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Karthik Rajaraman ,  Mihir Narendra Mody ,  Prithvi Y.A. ,  Deepshikha Gusain ,  Niraj Nandan ,  Mohd Asif Farooqui

IPC: G06F8/654

Abstract: Systems and methods for updating firmware may include using wait states to reduce or eliminate polling by an executing firmware component. An example includes dedicated firmware update hardware logic components, including a firmware update processing unit that executes firmware update code. The firmware update code may be paused between request of a hardware event and completion of a hardware event and under control of one or more of the hardware logic components. Once a hardware event has been completed, a hardware logic component may determine completion and, in response, restart execution of the firmware update code.

公开(公告)号：US20250103244A1

公开(公告)日：2025-03-27

申请号：US18371338

申请日：2023-09-21

Applicant: Texas Instruments Incorporated

Inventor： Vignesh Raghavendra ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Sai Karthik Rajaraman ,  Shailesh Ganapat Ghotgalkar ,  Mohammad Asif Farooqui

IPC: G06F3/06

Abstract: An example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. The example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. Additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.