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    LOCKSTEP COMPARATORS AND RELATED METHODS
    1.
    发明申请
    LOCKSTEP COMPARATORS AND RELATED METHODS 有权

    公开(公告)号：US20230068811A1

    公开(公告)日：2023-03-02

    申请号：US18047511

    申请日：2022-10-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

    IPC: G01R31/3177 ,  H03K5/24 ,  H03K19/003 ,  H03K3/037

    Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

    COMMUNICATION INTERFACE CONTROLLER WITH OUTPUT MONITORING
    2.
    发明申请
    COMMUNICATION INTERFACE CONTROLLER WITH OUTPUT MONITORING 有权

    公开(公告)号：US20250165416A1

    公开(公告)日：2025-05-22

    申请号：US18512210

    申请日：2023-11-17

    Applicant: Texas Instruments Incorporated

    Inventor： Ashish Vanjari ,  Mohammed Arif ,  Shailesh Ganapat Ghotgalkar

    IPC: G06F13/24 ,  G06F13/16

    Abstract: In described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides to the transceiver and the bus monitor an instruction that indicates an instructed target address, a read/write flag, and a memory address. The transceiver provides to the first pin and the bus monitor a clock signal, and provides to the second pin and the bus monitor a message so that the message includes a messaged target address, the read/write flag, and the memory address. The bus monitor compares the instructed target address to the messaged target address, and provides a signal to the processor in response to the comparison.

    Phase-locked loop slip detector
    4.
    发明授权
    Phase-locked loop slip detector 有权

    公开(公告)号：US11133807B2

    公开(公告)日：2021-09-28

    申请号：US16703232

    申请日：2019-12-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das ,  Jiankun Hu

    IPC: H03L7/089 ,  H03L7/095 ,  H03L7/087

    Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

    Data flow control for multi-chip select
    5.
    发明授权
    Data flow control for multi-chip select 有权

    公开(公告)号：US10817257B2

    公开(公告)日：2020-10-27

    申请号：US16390780

    申请日：2019-04-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shailesh Ganapat Ghotgalkar

    IPC: G06F5/14 ,  G06F3/06 ,  G06F5/06

    Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

    Phase-locked loop slip detector
    6.
    发明授权
    Phase-locked loop slip detector 有权

    公开(公告)号：US12052021B2

    公开(公告)日：2024-07-30

    申请号：US17931165

    申请日：2022-09-12

    Applicant: Texas Instruments Incorporated

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das ,  Jiankun Hu

    IPC: H03L7/089 ,  H03L7/087 ,  H03L7/095

    CPC classification number: H03L7/0891 ,  H03L7/087 ,  H03L7/095

    Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

    SELF-DIAGNOSTIC COUNTER
    8.
    发明申请
    SELF-DIAGNOSTIC COUNTER 有权

    公开(公告)号：US20220209776A1

    公开(公告)日：2022-06-30

    申请号：US17138569

    申请日：2020-12-30

    Applicant: Texas Instruments Incorporated

    Inventor： Shailesh Ganapat Ghotgalkar ,  Prasanth Viswanathan Pillai ,  Maheedhar Janaki Jalasutram

    IPC: H03K23/00 ,  G06F1/04

    Abstract: In described examples, a counter system includes a counter, a parity detector, a toggle flop, and a comparator. The counter iterates a count through a set of binary states in response to a clock signal, so that a binary value of a single bit of the count changes at each iteration. The parity detector detects the parity of the count. The toggle flop output is coupled to the toggle flop input. The toggle flop outputs a binary flop value. The binary flop value toggles between zero and one in response to the toggle flop input and the clock signal. The comparator compares the parity of the count and the toggle flop output, and outputs a first comparator value if the parity of the count and the toggle flop output are the same, and a second comparator value if the parity of the count and the toggle flop output are different.

    Phase lock loop reference loss detection
    9.
    发明授权
    Phase lock loop reference loss detection 有权

    公开(公告)号：US10727841B2

    公开(公告)日：2020-07-28

    申请号：US16167440

    申请日：2018-10-22

    Applicant: Texas Instruments Incorporated

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

    IPC: H03L7/087 ,  H03L7/099

    Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

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