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公开(公告)号：US10965279B2
公开(公告)日：2021-03-30
申请号：US16360927
申请日：2019-03-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yogesh Kumar Ramadass , Bhushan Talele , Shailendra Kumar Baranwal , Yinglai Xia , Junmin Jiang
Abstract: A multi-level ramp generator comprises three ramp generators. The first ramp generator generates a first ramp signal, comprising a sawtooth voltage waveform with a first common mode voltage and a first peak to peak voltage. The second ramp generator generates a second ramp signal, comprising a sawtooth voltage waveform with a second common mode voltage and a second peak-to-peak voltage. The third ramp generator generates a third ramp signal, comprising a sawtooth voltage waveform with a third common mode voltage and the second peak-to-peak voltage. The second and third ramp signals are in phase with each other and the first ramp signal is 180° out of phase with the second and third ramp signals. In some implementations, each of the first, second, and third ramp generators comprise a respective delay locked loop and a respective voltage controlled oscillator.
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公开(公告)号：US20180152109A1
公开(公告)日：2018-05-31
申请号：US15363188
申请日：2016-11-29
Applicant: Texas Instruments Incorporated
Inventor： Shailendra Kumar Baranwal , Maurizio Granato , Giovanni Frattini
CPC classification number: H02M3/33592 , H02M1/08 , H02M3/33553 , H02M2001/0058
Abstract: An electronic device, which includes an H-bridge circuit and a miniaturized transformer that is coupled to operate at VHF frequency, and a driver circuit for an n-type power transistor of the H-bridge circuit are disclosed. The driver circuit includes a first p-type transistor and an n-type transistor coupled between an upper rail and a lower rail, with an output taken between the drains of the first p-type transistor and the n-type transistor being coupled to a gate of the n-type power transistor. The driver circuit also includes a sample-and-hold capacitor coupled to capture a drain voltage for the first n-type power transistor on a first edge of a control signal for the first n-type power transistor and a comparator coupled to compare the captured drain voltage to a lower rail on a given edge of a clock signal and to provide a comparator value. The driver circuit also includes an up/down counter, which is coupled to receive the comparator value, to adjust a counter value responsive to receiving the comparator value and to output the counter value, and a first timing circuit that is coupled to receive the counter value and to send an adjustable pulse towards a gate of the first p-type transistor and a gate of the n-type transistor.
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公开(公告)号：US11336193B2
公开(公告)日：2022-05-17
申请号：US16822268
申请日：2020-03-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Maurizio Granato , Giovanni Frattini , Shailendra Kumar Baranwal
Abstract: In described examples, an isolated DC-DC converter includes: an input node for receiving an input voltage; a transformer including a primary side having first and second terminals and a primary side ground; and first and second low-side switches. The first low-side switch is coupled between the first terminal and the primary side ground. The second low-side switch is coupled between the second terminal and the primary side ground. A first voltage is across the first low-side switch, and a second voltage is across the second low-side switch. Also, the isolated DC-DC converter includes first and second high-side switches. The first high-side switch is coupled between the first terminal and the input node. The second high-side switch is coupled between the second terminal and the input node. Further, the isolated DC-DC converter includes a switch controller.
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公开(公告)号：US10014760B2
公开(公告)日：2018-07-03
申请号：US15395370
申请日：2016-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shailendra Kumar Baranwal , Alan Stephen Bass , Vighnesh Rudra Das , Anant Shankar Kamath , Abhijeeth Aarey Premanath
CPC classification number: H02M1/08 , H02M1/36 , H02M3/33515 , H03K17/163 , H03K17/164
Abstract: One example includes a switch circuit. The switch circuit includes a transistor configured to activate in response to an activation voltage at an activation terminal of the transistor. The switch circuit also includes a current source coupled to the activation terminal and being configured to generate an activation current. The switch circuit further includes a driver control circuit interconnecting the activation terminal and a voltage rail. The driver control circuit includes digital counter logic configured to cycle through a predetermined number of count values based on an oscillator signal. The driver control circuit is configured to adjust an amplitude of the activation voltage at each of the predetermined number of count values based on the activation current to provide a soft-start activation of the transistor.
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公开(公告)号：US20220302908A1
公开(公告)日：2022-09-22
申请号：US17832280
申请日：2022-06-03
Applicant: Texas Instruments Incorporated
Inventor： Yinglai Xia , Shailendra Kumar Baranwal , Yogesh Kumar Ramadass , Junmin Jiang
Abstract: A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.
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Patent Agency Ranking
公开(公告)号：US10886881B2
公开(公告)日：2021-01-05
申请号：US16360703
申请日：2019-03-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yinglai Xia , Shailendra Kumar Baranwal , Junmin Jiang , Yogesh Kumar Ramadass
Abstract: An amplifier comprises eight transistors: the first coupled to a linked node and to a positive output node, the second coupled to the linked node and to a negative output node, the third coupled to the positive output node and a common potential, the fourth coupled to the negative output node and the common potential, the fifth coupled to a battery node, the sixth coupled to the fifth transistor and to the positive output node, the seventh coupled to the battery node, and the eighth coupled to the seventh transistor and to the negative output node. The amplifier also includes a charge pump to convert the battery voltage to an increased voltage on the linked node. The charge pump includes capacitors and operates at a lower frequency in lower power mode and a higher frequency in higher power mode to increase power provided to the linked node.
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公开(公告)号：US20200287473A1
公开(公告)日：2020-09-10
申请号：US16822268
申请日：2020-03-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Maurizio Granato , Giovanni Frattini , Shailendra Kumar Baranwal
Abstract: In described examples, an isolated DC-DC converter includes: an input node for receiving an input voltage; a transformer including a primary side having first and second terminals and a primary side ground; and first and second low-side switches. The first low-side switch is coupled between the first terminal and the primary side ground. The second low-side switch is coupled between the second terminal and the primary side ground. A first voltage is across the first low-side switch, and a second voltage is across the second low-side switch. Also, the isolated DC-DC converter includes first and second high-side switches. The first high-side switch is coupled between the first terminal and the input node. The second high-side switch is coupled between the second terminal and the input node. Further, the isolated DC-DC converter includes a switch controller.
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公开(公告)号：US10439482B2
公开(公告)日：2019-10-08
申请号：US15713204
申请日：2017-09-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: In an embodiment, an adaptive drive strength switching converter includes a driver and a control loop coupled to the driver. In an embodiment, the control loop includes a peak detector, a comparator coupled to an output of the peak detector, a counter coupled to an output of the comparator, and a digital-to-analog converter (DAC) coupled to an output of the comparator.
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公开(公告)号：US20240088878A1
公开(公告)日：2024-03-14
申请号：US18512158
申请日：2023-11-17
Applicant: Texas Instruments Incorporated
Inventor： Yinglai Xia , Shailendra Kumar Baranwal , Yogesh Kumar Ramadass , Junmin Jiang
CPC classification number: H03K4/08 , H03F3/2173 , H03L7/081 , H03L7/0891 , H03L7/099 , H03F2200/03 , H03K19/20
Abstract: In one example, an apparatus comprises a power stage having a first power stage input, a second power stage input, and a power stage output. The apparatus also comprises a modulator circuit having a first ramp input, a second ramp input, a modulator input, a first modulator output, and a second modulator output, the first modulator output coupled to the first power stage input, and the second modulator output coupled to the second power stage input. The apparatus also comprises a multi-level ramp generator having a first ramp output and a second ramp output, the first ramp output coupled to the first ramp input, and the second ramp output coupled the second ramp input.
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公开(公告)号：US11824543B2
公开(公告)日：2023-11-21
申请号：US17832280
申请日：2022-06-03
Applicant: Texas Instruments Incorporated
Inventor： Yinglai Xia , Shailendra Kumar Baranwal , Yogesh Kumar Ramadass , Junmin Jiang
CPC classification number: H03K4/08 , H03F3/2173 , H03L7/081 , H03L7/0891 , H03L7/099 , H03F2200/03 , H03K19/20
Abstract: A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.
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