公开(公告)号：US20190067017A1

公开(公告)日：2019-02-28

申请号：US15864802

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jian Jun Kong ,  She Yu Tang ,  Tian Yi Zhang ,  Qin Xu Yu ,  Sheng Pin Yang

IPC: H01L21/304 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/683

Abstract: In some embodiments, a method includes wet-etching a first film layer of a plurality of film layers stacked on a semiconductor substrate, the wet-etching of the first film layer performed using a first chemical, where the first film layer is an outermost film layer stacked on the semiconductor substrate. The method further includes wet-etching a second film layer of the plurality of film layers using a second chemical. The method also includes using a mechanical grinding wheel to grind the semiconductor substrate to reduce a thickness of the semiconductor substrate.

公开(公告)号：US10249504B2

公开(公告)日：2019-04-02

申请号：US15864802

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jian Jun Kong ,  She Yu Tang ,  Tian Yi Zhang ,  Qin Xu Yu ,  Sheng Pin Yang

IPC: H01L21/304 ,  H01L21/311 ,  H01L21/683 ,  H01L21/3213

Abstract: In some embodiments, a method includes wet-etching a first film layer of a plurality of film layers stacked on a semiconductor substrate, the wet-etching of the first film layer performed using a first chemical, where the first film layer is an outermost film layer stacked on the semiconductor substrate. The method further includes wet-etching a second film layer of the plurality of film layers using a second chemical. The method also includes using a mechanical grinding wheel to grind the semiconductor substrate to reduce a thickness of the semiconductor substrate.

公开(公告)号：US20240096814A1

公开(公告)日：2024-03-21

申请号：US17948343

申请日：2022-09-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Guoyong Zhang ,  She Yu Tang ,  Shu Min Ma ,  Lei Zhang ,  Peng Hu ,  Fei Yu

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426

Abstract: The present disclosure generally relates to semiconductor processing in which an alignment mark is formed. An example is method of semiconductor processing. First and second recesses are formed in a semiconductor substrate. A conformal dielectric layer is formed in the first and second recesses and over the semiconductor substrate. A fill material is formed over the conformal dielectric layer in the first recess and over the conformal dielectric layer in the second recess. The fill material fills at least the first recess over the conformal dielectric layer. The fill material in the first and second recesses is recessed to below a top surface of the conformal dielectric layer. The recessed fill material in the first and second recesses is etched. Exposed portions of the conformal dielectric layer are etched. The second recess including the conformal dielectric layer and the recessed fill material disposed therein forms an alignment mark.

公开(公告)号：US10566204B2

公开(公告)日：2020-02-18

申请号：US16282344

申请日：2019-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jian Jun Kong ,  She Yu Tang ,  Tian Yi Zhang ,  Qin Xu Yu ,  Sheng Pin Yang

IPC: H01L21/304 ,  H01L21/311 ,  H01L21/683 ,  H01L21/3213

Abstract: In some embodiments, a method of forming an integrated circuit includes providing a semiconductor substrate having an electronic circuit formed on a front side, and having a first material layer located over a second side of the substrate and a second material layer located between the first material layer and the second side. At least a portion of the first material layer is removed using a first chemical etching process, thereby exposing the second material layer. At least a portion of the second material layer is removed using a second chemical etching process. A portion of the substrate is then mechanically removed from the second side.

公开(公告)号：US20210159189A1

公开(公告)日：2021-05-27

申请号：US16840705

申请日：2020-04-06

Applicant: Texas Instruments Incorporated

Inventor： Qin Xu Yu ,  Jian Jun Kong ,  She Yu Tang ,  Yun Fu An

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/552 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

Abstract: In a described example, an electrical apparatus includes: a metal layer formed over a non-device side of a semiconductor device die, the semiconductor device die having devices formed on a device side of the semiconductor device die opposite the non-device side; a first side of the metal layer bonded to a die mount pad on a package substrate; a second side of the metal layer formed over a roughened surface on the non-device side of the semiconductor device die, the roughened surface having an average surface roughness (Ra) between 40 nm and 500 nm; bond pads on the semiconductor device die electrically coupled to conductive leads on the package substrate; and mold compound covering at least a portion of the semiconductor device die and at least a portion of the conductive leads.