公开(公告)号：US11206036B2

公开(公告)日：2021-12-21

申请号：US16709809

申请日：2019-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rahul Vijay Kulkarni ,  Abhijeet Gopal Godbole ,  Shridhar Atmaram More

IPC: H03M1/10 ,  G01R31/40 ,  H03K5/24

Abstract: An integrated self-test mechanism for monitoring an analog-to-digital converter (ADC), a reference voltage (Vref) source associated with the ADC, a low-dropout regulator (LDO), or a power supply is provided. In one example, an ADC that is associated with an integrated circuit (IC) can monitor its own Vref, the voltage (VLBO) of an LDO associated with the IC, or the voltage (AVDD) provided to an electrical coupling mechanism in the IC that is coupled to a power supply associated with the IC. The ADC can generate a digital output code based, at least in part, on the Vref and one or more of the VLBO and the AVDD. The digital output code can be used to determine whether one or more of the ADC, the Vref source, the LDO, and the power supply is malfunctioning or nonoperational.

公开(公告)号：US10673455B2

公开(公告)日：2020-06-02

申请号：US15977910

申请日：2018-05-11

Applicant: Texas Instruments Incorporated

Inventor： Rahul Vijay Kulkarni ,  Shridhar Atmaram More ,  Kaustubh Ulhas Gadgil

IPC: H03M1/12 ,  H03M1/46

Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.

公开(公告)号：US20200252077A1

公开(公告)日：2020-08-06

申请号：US16856194

申请日：2020-04-23

Applicant: Texas Instruments Incorporated

Inventor： Rahul Vijay Kulkarni ,  Shridhar Atmaram More ,  Kaustubh Ulhas Gadgil

IPC: H03M1/46

Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.

公开(公告)号：US11139823B2

公开(公告)日：2021-10-05

申请号：US16856194

申请日：2020-04-23

Applicant: Texas Instruments Incorporated

Inventor： Rahul Vijay Kulkarni ,  Shridhar Atmaram More ,  Kaustubh Ulhas Gadgil

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/38

Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.