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公开(公告)号：US11206036B2
公开(公告)日：2021-12-21
申请号：US16709809
申请日：2019-12-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rahul Vijay Kulkarni , Abhijeet Gopal Godbole , Shridhar Atmaram More
Abstract: An integrated self-test mechanism for monitoring an analog-to-digital converter (ADC), a reference voltage (Vref) source associated with the ADC, a low-dropout regulator (LDO), or a power supply is provided. In one example, an ADC that is associated with an integrated circuit (IC) can monitor its own Vref, the voltage (VLBO) of an LDO associated with the IC, or the voltage (AVDD) provided to an electrical coupling mechanism in the IC that is coupled to a power supply associated with the IC. The ADC can generate a digital output code based, at least in part, on the Vref and one or more of the VLBO and the AVDD. The digital output code can be used to determine whether one or more of the ADC, the Vref source, the LDO, and the power supply is malfunctioning or nonoperational.
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公开(公告)号：US20210175891A1
公开(公告)日：2021-06-10
申请号：US16706399
申请日：2019-12-06
Applicant: Texas Instruments Incorporated
Inventor： Kaustubh Gadgil , Rahul Vijay Kulkarni
Abstract: A method for testing an A/D converter with a built-in diagnostic circuit with a user supplied variable input voltage includes generating a charge by a binary-weighted capacitor array responsive to an external voltage and a user specified code. The method further includes applying the charge to a first input of a voltage comparator and applying a bias voltage to a second input of the voltage comparator, and generating, by the voltage comparator, a comparison voltage responsive to the applied charge and the bias voltage. The method also includes applying the comparison voltage to an input of a successive approximation register and generating, by the successive approximation register, an approximate digital code responsive to the comparison voltage. The method also includes determining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits.
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公开(公告)号：US11101811B2
公开(公告)日：2021-08-24
申请号：US16706399
申请日：2019-12-06
Applicant: Texas Instruments Incorporated
Inventor： Kaustubh Gadgil , Rahul Vijay Kulkarni
Abstract: A method for testing an A/D converter with a built-in diagnostic circuit with a user supplied variable input voltage includes generating a charge by a binary-weighted capacitor array responsive to an external voltage and a user specified code. The method further includes applying the charge to a first input of a voltage comparator and applying a bias voltage to a second input of the voltage comparator, and generating, by the voltage comparator, a comparison voltage responsive to the applied charge and the bias voltage. The method also includes applying the comparison voltage to an input of a successive approximation register and generating, by the successive approximation register, an approximate digital code responsive to the comparison voltage. The method also includes determining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits.
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公开(公告)号：US10673455B2
公开(公告)日：2020-06-02
申请号：US15977910
申请日：2018-05-11
Applicant: Texas Instruments Incorporated
Inventor： Rahul Vijay Kulkarni , Shridhar Atmaram More , Kaustubh Ulhas Gadgil
Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.
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公开(公告)号：US10236902B1
公开(公告)日：2019-03-19
申请号：US15874100
申请日：2018-01-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shridhar More , Rahul Vijay Kulkarni
Abstract: An analog-to-digital converter includes an input terminal, a digital-to-analog converter, a comparator, and successive approximation circuitry. The input terminal is configured to receive a multi-bit digital threshold value from circuitry external to the analog-to-digital converter. The successive approximation circuitry is coupled to the comparator and the digital-to-analog converter. The successive approximation circuitry is configured to operate in a comparison mode and a conversion mode, and to provide the multi-bit digital threshold value to the digital-to-analog converter while operating in the comparison mode. The comparator is coupled to the digital-to-analog converter and the successive approximation circuitry. The comparator is configured to output a signal that indicates whether an analog input signal exceeds an analog threshold signal corresponding to the multi-bit digital threshold value.
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Patent Agency Ranking
公开(公告)号：US10892768B2
公开(公告)日：2021-01-12
申请号：US15700379
申请日：2017-09-11
Applicant: Texas Instruments Incorporated
Abstract: Disclosed examples include a method and automated test system for testing an ADC. The method includes computing an ADC noise value based on a first set of data values sampled while the ADC input terminals are shorted, computing a first system noise value based on a second set of data values sampled while a test circuit signal source applies zero volts to the ADC through a signal chain, computing a signal chain noise value based on the first system noise value and the ADC noise value, computing a measured SNR value based on a third set of data values sampled while the test circuit signal source applies a non-zero source voltage signal to the signal chain, computing a second system noise value based on the measured SNR value, and computing an ADC SNR value based on the second system noise value and the signal chain noise value.
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公开(公告)号：US20200252077A1
公开(公告)日：2020-08-06
申请号：US16856194
申请日：2020-04-23
Applicant: Texas Instruments Incorporated
Inventor： Rahul Vijay Kulkarni , Shridhar Atmaram More , Kaustubh Ulhas Gadgil
IPC: H03M1/46
Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.
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公开(公告)号：US20190081634A1
公开(公告)日：2019-03-14
申请号：US15700379
申请日：2017-09-11
Applicant: Texas Instruments Incorporated
IPC: H03M1/10
Abstract: Disclosed examples include a method and automated test system for testing an ADC. The method includes computing an ADC noise value based on a first set of data values sampled while the ADC input terminals are shorted, computing a first system noise value based on a second set of data values sampled while a test circuit signal source applies zero volts to the ADC through a signal chain, computing a signal chain noise value based on the first system noise value and the ADC noise value, computing a measured SNR value based on a third set of data values sampled while the test circuit signal source applies a non-zero source voltage signal to the signal chain, computing a second system noise value based on the measured SNR value, and computing an ADC SNR value based on the second system noise value and the signal chain noise value.
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公开(公告)号：US11206035B2
公开(公告)日：2021-12-21
申请号：US16702090
申请日：2019-12-03
Applicant: Texas Instruments Incorporated
Inventor： Rahul Vijay Kulkarni , Shridhar More , Amal Kumar Kundu , Minkle Eldho Paul
Abstract: An analog to digital (A/D) converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals coupled to a sample and hold (S/H) output. The A/D converter also includes a voltage comparator having a first input coupled to the S/H output and having a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage. The A/D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array.
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公开(公告)号：US11139823B2
公开(公告)日：2021-10-05
申请号：US16856194
申请日：2020-04-23
Applicant: Texas Instruments Incorporated
Inventor： Rahul Vijay Kulkarni , Shridhar Atmaram More , Kaustubh Ulhas Gadgil
Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.
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