公开(公告)号：US10691074B2

公开(公告)日：2020-06-23

申请号：US16403774

申请日：2019-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Yao ,  Sinjeet Dhanvantray Parekh

IPC: G04F10/00 ,  H03L7/197

Abstract: A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

公开(公告)号：US10727846B2

公开(公告)日：2020-07-28

申请号：US16582341

申请日：2019-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayawardan Janardhanan ,  Christopher Andrew Schell ,  Arvind Sridhar ,  Sinjeet Dhanvantray Parekh

IPC: H03L7/093 ,  H03L7/14 ,  H03L7/087 ,  H03L7/083

Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

公开(公告)号：US10686456B2

公开(公告)日：2020-06-16

申请号：US16218970

申请日：2018-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayawardan Janardhanan ,  Christopher Andrew Schell ,  Sinjeet Dhanvantray Parekh

IPC: H03L7/099 ,  G04F10/00 ,  H03L7/093 ,  H03L7/083

Abstract: A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.