公开(公告)号：US11663095B2

公开(公告)日：2023-05-30

申请号：US17372599

申请日：2021-07-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saya Goud Langadi ,  Srinivasa Chakravarthy Bs

IPC: G06F11/16 ,  G06F11/10

CPC classification number: G06F11/167 ,  G06F11/1044 ,  G06F11/1645

Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.

公开(公告)号：US11061783B2

公开(公告)日：2021-07-13

申请号：US16396941

申请日：2019-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saya Goud Langadi ,  Srinivasa Chakravarthy Bs

IPC: G06F11/16 ,  G06F11/10

Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.