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    Programmable Interface Circuit to Operate Sensors
    1.
    发明申请
    Programmable Interface Circuit to Operate Sensors 有权

    公开(公告)号：US20250021511A1

    公开(公告)日：2025-01-16

    申请号：US18220353

    申请日：2023-07-11

    Applicant: Texas Instruments Incorporated

    Inventor： Saya Goud Langadi

    IPC: G06F13/42

    Abstract: A microcontroller may include a programmable interface circuit to operate one or more sensors. The interface circuit may include a first set of storage to store a first set of values. The first set of values may specify a period and a set of transitions for a first signal. The interface circuit may include one or more second sets of storage to store one or more second sets of values respectively. The second sets of values may each specify a period and a set of transitions for a respective one of one or more second signals. The interface circuit may include a signal generator operatively coupled to the first and second sets of storage to generate the first and second signals based on the first and second sets of values.

    INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE
    4.
    发明申请
    INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE 有权

    公开(公告)号：US20220214880A1

    公开(公告)日：2022-07-07

    申请号：US17143989

    申请日：2021-01-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Saya Goud Langadi ,  Venkatesh Natarajan ,  Alexander Tessarolo

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

    Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.

    Missing clock circuit switching clock from second to first clock
    5.
    发明授权
    Missing clock circuit switching clock from second to first clock 有权
    从第二个到第一个时钟，缺少时钟电路切换时钟

    公开(公告)号：US08803554B2

    公开(公告)日：2014-08-12

    申请号：US13657142

    申请日：2012-10-22

    Applicant: Texas Instruments Incorporated

    Inventor： Saya Goud Langadi

    IPC: H03K19/096

    CPC classification number: H03K5/19 ,  G06F1/08 ,  H03K5/1252

    Abstract: A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output.

    Abstract translation: 无毛刺时钟切换电路包括第一使能同步逻辑，其响应于来自第一使能生成逻辑的第一使能而产生第一时钟使能。 时钟切换电路包括第二使能同步逻辑，其响应于来自第二使能产生逻辑的第二使能而产生第二时钟使能。 如果第二使能是逻辑高，逻辑门耦合到第二使能同步逻辑的输出，其选择第二时钟信号作为逻辑门输出。 优先多路复用器接收第一时钟信号，第一使能和逻辑门输出。 多路复用器被配置为如果第一使能是逻辑高，则选择第一时钟信号作为时钟输出，而与逻辑门输出无关。

    PROCESSOR WITH HARDWARE-INTEGRATED MEMORY ACCESS PROTECTION
    6.
    发明申请
    PROCESSOR WITH HARDWARE-INTEGRATED MEMORY ACCESS PROTECTION 有权

    公开(公告)号：US20250021242A1

    公开(公告)日：2025-01-16

    申请号：US18771764

    申请日：2024-07-12

    Applicant: Texas Instruments Incorporated

    Inventor： David Foley ,  Saya Goud Langadi ,  Alexander Tessarolo ,  Venkatesh Natarajan

    IPC: G06F3/06

    Abstract: In described examples, an integrated circuit (IC) includes a memory and a processor coupled to the memory. The processor is configured to execute a discontinuity instruction, which specifies a memory address, to transition from executing according to a first stack pointer to executing according to a second stack pointer. The first stack pointer is copied from an active stack register to an inactive first stack pointer register. The processor determines whether the specified memory address stores a stack entry instruction that corresponds to the discontinuity instruction. If it does, the second stack pointer is copied from the inactive second stack pointer register to the active stack register, and the processor executes the stack entry instruction and begins execution according to the second stack pointer.

    Error detection circuit
    7.
    发明授权
    Error detection circuit 有权

    公开(公告)号：US11663095B2

    公开(公告)日：2023-05-30

    申请号：US17372599

    申请日：2021-07-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Saya Goud Langadi ,  Srinivasa Chakravarthy Bs

    IPC: G06F11/16 ,  G06F11/10

    CPC classification number: G06F11/167 ,  G06F11/1044 ,  G06F11/1645

    Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.

    Multi master arbitration scheme in a system on chip
    8.
    发明授权
    Multi master arbitration scheme in a system on chip 有权

    公开(公告)号：US09910803B2

    公开(公告)日：2018-03-06

    申请号：US14306970

    申请日：2014-06-17

    Applicant: Texas Instruments Incorporated

    Inventor： Saya Goud Langadi

    IPC: G06F13/12 ,  G06F13/37 ,  G06F13/16

    CPC classification number: G06F13/37 ,  G06F13/1657

    Abstract: A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.

    METHODS AND APPARATUS TO SEQUENCE BRANCH OPERATIONS
    9.
    发明申请
    METHODS AND APPARATUS TO SEQUENCE BRANCH OPERATIONS 有权

    公开(公告)号：US20250045052A1

    公开(公告)日：2025-02-06

    申请号：US18587432

    申请日：2024-02-26

    Applicant: Texas Instruments Incorporated

    Inventor： Venkatesh Natarajan ,  Saya Goud Langadi ,  Alexander Tessarolo

    IPC: G06F9/30 ,  G06F9/38

    Abstract: An example apparatus includes: address generation circuitry configured to generate a first address associated with a first packet, a second address associated with a second packet, and a third address associated with a third packet, wherein: the first packet includes a branch instruction; the branch instruction includes a first field that specifies a branch target, and a second field that is different from the first field; and the third packet includes the branch target of the branch instruction; buffer circuitry configured to receive the first packet, the second packet, and the third packet; decoder circuitry coupled to the buffer circuitry, the decoder circuitry configured to decode the first packet, the second packet, and the third packet; discontinuity controller circuitry coupled to the buffer circuitry and the decoder circuitry and configured to determine whether to cause the address generation circuitry to generate the second address.

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