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公开(公告)号:US20170201399A1
公开(公告)日:2017-07-13
申请号:US15354149
申请日:2016-11-17
Applicant: Texas Instruments Incorporated
Abstract: An isolator chip includes a transmitter circuit coupled to provide differential output signals to respective first terminals of a first and a second capacitor and a receiver circuit coupled to receive the differential output signals from respective second terminals of the first and second capacitors. The transmitter circuit includes a voltage-clamping circuit coupled to receive an input signal and to provide a clamped signal, an oscillator coupled to receive the clamped signal and to provide the differential output signals, and a common mode transient immunity (CMTI) circuit that couples respective first terminals of the first and second capacitors to a lower rail responsive to the clamped signal being low.
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公开(公告)号:US11677315B2
公开(公告)日:2023-06-13
申请号:US17103176
申请日:2020-11-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Srinivasa Rao Madala , Suvadip Banerjee , Sudhir Komarla Adinarayana , Tarunvir Singh
CPC classification number: H02M1/44 , H02M3/24 , H02M3/33515
Abstract: A system includes a switching converter, an input voltage source coupled to an input of the switching converter, and a load coupled to an output of the switching converter. The system also includes a load sense circuit coupled to the load and configured to provide a load sense signal. The system also includes an oscillator coupled to the switching converter and configured to provide a spread spectrum modulated (SSM) clock signal to the switching converter, wherein a frequency of the SSM clock signal varies as a function of the load sense signal.
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公开(公告)号:US10819543B2
公开(公告)日:2020-10-27
申请号:US15354149
申请日:2016-11-17
Applicant: Texas Instruments Incorporated
IPC: H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06 , H01C7/12 , H04L27/04 , H04B3/30 , H04B1/04 , H04B1/40 , H04B1/69
Abstract: An isolator chip includes a transmitter circuit coupled to provide differential output signals to respective first terminals of a first and a second capacitor and a receiver circuit coupled to receive the differential output signals from respective second terminals of the first and second capacitors. The transmitter circuit includes a voltage-clamping circuit coupled to receive an input signal and to provide a clamped signal, an oscillator coupled to receive the clamped signal and to provide the differential output signals, and a common mode transient immunity (CMTI) circuit that couples respective first terminals of the first and second capacitors to a lower rail responsive to the clamped signal being low.
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