公开(公告)号：US20220038079A1

公开(公告)日：2022-02-03

申请号：US17377087

申请日：2021-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kashyap Jayendra Barot ,  Suvadip Banerjee ,  Sreeram Subramanyam Nasum

IPC: H03K3/0233 ,  H02M1/00 ,  H02M1/14 ,  H02M1/08 ,  H02M3/335

Abstract: An apparatus includes a first control circuit having an output and including a first comparator and a second control circuit coupled to the output of the first control circuit. The second control circuit includes a second comparator configured to: compare a first value to a reference frequency value, the first value indicating a frequency of a signal at the output of the first control circuit; and provide an adjustment value to change a hysteresis window of the first comparator.

公开(公告)号：US20240136989A1

公开(公告)日：2024-04-25

申请号：US17972518

申请日：2022-10-23

Applicant: Texas Instruments Incorporated

Inventor： Harsh Sheokand ,  Tarunvir Singh ,  Anant Kamath ,  Suvadip Banerjee

IPC: H03F3/45

CPC classification number: H03F3/45654 ,  H03F3/45183 ,  H03F2203/45526

Abstract: A system includes an operational amplifier which includes a first amplifier input, a second amplifier input and an amplifier output. The system includes a first switch which includes a first terminal and includes a second terminal coupled to the first amplifier input. The system includes a second switch which includes a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input. The system includes a first bias current source coupled between the first amplifier input and a common potential and includes a second bias current source coupled between the first terminal of the first switch and the common potential. The system includes a feedback path between the amplifier output and the first amplifier input.

公开(公告)号：US11677315B2

公开(公告)日：2023-06-13

申请号：US17103176

申请日：2020-11-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivasa Rao Madala ,  Suvadip Banerjee ,  Sudhir Komarla Adinarayana ,  Tarunvir Singh

IPC: H02M3/24 ,  H02M1/44 ,  H02M3/335

CPC classification number: H02M1/44 ,  H02M3/24 ,  H02M3/33515

Abstract: A system includes a switching converter, an input voltage source coupled to an input of the switching converter, and a load coupled to an output of the switching converter. The system also includes a load sense circuit coupled to the load and configured to provide a load sense signal. The system also includes an oscillator coupled to the switching converter and configured to provide a spread spectrum modulated (SSM) clock signal to the switching converter, wherein a frequency of the SSM clock signal varies as a function of the load sense signal.

公开(公告)号：US11671138B2

公开(公告)日：2023-06-06

申请号：US17489483

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： RR Manikandan ,  Kumar Anurag Shrivastava ,  Robert Floyd Payne ,  Anant Shankar Kamath ,  Swaminathan Sankaran ,  Kishalay Datta ,  Siraj Akhtar ,  Mark Edward Wentroble ,  Suvadip Banerjee ,  Rakesh Hariharan ,  Gurumurti Kailaschandra Avhad

IPC: H03K5/24 ,  H04B1/44 ,  H03K3/017 ,  H04L27/06 ,  H04L27/04

CPC classification number: H04B1/44 ,  H03K3/017 ,  H03K5/24 ,  H04L27/04 ,  H04L27/066

Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

公开(公告)号：US11841810B2

公开(公告)日：2023-12-12

申请号：US17244370

申请日：2021-04-29

Applicant: Texas Instruments Incorporated

Inventor： Suvadip Banerjee ,  Sreeram Subramanyam Nasum ,  Anant Shankar Kamath

IPC: G06F13/20 ,  G06F13/40 ,  H03K17/687 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/4086 ,  H03K17/6871 ,  G06F13/4282 ,  G06F2213/0016

Abstract: A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.

公开(公告)号：US11574884B2

公开(公告)日：2023-02-07

申请号：US17162189

申请日：2021-01-29

Applicant: Texas Instruments Incorporated

Inventor： Suvadip Banerjee ,  John Paul Tellkamp

IPC: H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H01R9/00 ,  H05K7/00 ,  B23K31/02 ,  H01L23/00 ,  H01L21/48 ,  H01L23/528 ,  H01L23/488

Abstract: An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

公开(公告)号：US11552619B2

公开(公告)日：2023-01-10

申请号：US17377087

申请日：2021-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kashyap Jayendra Barot ,  Suvadip Banerjee ,  Sreeram Subramanyam Nasum

IPC: H03K3/0233 ,  H02M1/00 ,  H02M3/335 ,  H02M1/08 ,  H02M1/14

Abstract: An apparatus includes a first control circuit having an output and including a first comparator and a second control circuit coupled to the output of the first control circuit. The second control circuit includes a second comparator configured to: compare a first value to a reference frequency value, the first value indicating a frequency of a signal at the output of the first control circuit; and provide an adjustment value to change a hysteresis window of the first comparator.

公开(公告)号：US10761111B2

公开(公告)日：2020-09-01

申请号：US15989126

申请日：2018-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arun Adoni ,  Suvadip Banerjee ,  Sreeram Subramanyam Nasum ,  Prajkta Vyavahare

IPC: G01R1/067 ,  G01R31/28 ,  G01R35/00

Abstract: A system includes a controller for automated test equipment (ATE) contactor to interface with a device under test (DUT) including a power converter having a primary and secondary side, each side has an input/output (I/O) pin. The controller causes the ATE contactor to apply a load current on the secondary side of the power converter at a first value and vary the load current to a second value. The contactor receives first and second indications, at the first and second load currents, of a voltage on the primary side I/O pin, a voltage on the primary side of the power converter, an input current on the primary side of the power converter, a voltage on the secondary side I/O pin, and a voltage on the secondary side of the power converter. The controller determines a primary and secondary side ATE contactor resistances based on the first and second indications.

公开(公告)号：US12160169B2

公开(公告)日：2024-12-03

申请号：US17828470

申请日：2022-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anandha Ruban Tiruchengode Tirumurugga Bupathi ,  Suvadip Banerjee ,  Anant Kamath

IPC: H02M1/36 ,  H02M1/32 ,  H02M3/04

Abstract: Circuits and systems include a parallel resistor-capacitor (RC) network coupled between a pin and ground, and first and second transistors coupled in source follower configuration with a common gate coupling. The source of the first transistor is coupled to the pin. A first switch couples a drain of the first transistor to the common gate coupling during soft-start (SS) and decouples that connection during over current limit (OCL) sensing, and a second switch couples a drain of the second transistor to the common gate coupling during OCL sensing and decouples that connection during SS. A first current source is enabled deliver a constant current to the pin during SS. A second current source is enabled to generate a reference voltage at the source of the second transistor during OCL, which reference voltage is transferred to the pin by the source follower configuration. A comparator controls the switches to transition from SS to OCL sensing. The comparator output signal is based on a comparison of the voltage at the pin to a threshold voltage.

公开(公告)号：US20240195417A1

公开(公告)日：2024-06-13

申请号：US18525464

申请日：2023-11-30

Applicant: Texas Instruments Incorporated

Inventor： Avinash Shah ,  Kashyap Barot ,  Sreeram Nasum S ,  Kumar Anurag Shrivastava ,  Suvadip Banerjee

IPC: H03K19/017 ,  G05B19/05 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/01728 ,  G05B19/054 ,  H03K19/00361 ,  H03K19/00384 ,  H03K19/018557 ,  H03K19/017572

Abstract: An example apparatus includes: a current mirror having first and second outputs; oscillator circuitry including: a first transistor having a first terminal coupled to the first output of the current mirror, having a second terminal, and having a control terminal; and a second transistor having a first terminal coupled to the first output of the current mirror, having a second terminal coupled to the control terminal and the second terminal of the first transistor, and having a control terminal coupled to the second terminals of the first and second transistors; and current shunt circuitry having a terminal coupled to the second output of the current mirror.