FSM BASED CLOCK SWITCHING OF ASYNCHRONOUS CLOCKS

    公开(公告)号:US20230384820A1

    公开(公告)日:2023-11-30

    申请号:US17824695

    申请日:2022-05-25

    CPC classification number: G06F1/12 G06F1/08 G06F1/10

    Abstract: Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.

    GATED RING OSCILLATOR LINEARIZATION

    公开(公告)号:US20230031630A1

    公开(公告)日:2023-02-02

    申请号:US17390291

    申请日:2021-07-30

    Abstract: Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.

    GATED RING OSCILLATOR LINEARIZATION
    3.
    发明公开

    公开(公告)号:US20230418238A1

    公开(公告)日:2023-12-28

    申请号:US18466027

    申请日:2023-09-13

    CPC classification number: G04F10/005 H03K3/0315

    Abstract: Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.

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