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公开(公告)号：US09148316B2
公开(公告)日：2015-09-29
申请号：US13937925
申请日：2013-07-09
CPC分类号： H04L25/03057 , H04L25/03878 , H04L2025/0349 , H04L2025/03617
摘要： A decision feedback equalizer (DFE) circuit includes a first equalization path and a second equalization path. Each equalization path includes a summing node, a first latch, a second latch, a first feedback path, and a second feedback path. The first latch is configured to latch data received from the summing node. The second latch is configured to latch data received from the first latch. The first feedback path is configured to receive data from the second latch and to provide data to the summing node of the equalization path. The second feedback path is configured to receive data from the first latch and to provide data to the summing node of the other equalization path. The second feedback path provides up to a symbol interval for propagation of data between the summing nodes.
摘要翻译： 判决反馈均衡器（DFE）电路包括第一均衡路径和第二均衡路径。 每个均衡路径包括求和节点，第一锁存器，第二锁存器，第一反馈路径和第二反馈路径。 第一锁存器被配置为锁存从求和节点接收到的数据。 第二锁存器被配置为锁存从第一锁存器接收到的数据。 第一反馈路径被配置为从第二锁存器接收数据并且向均衡路径的求和节点提供数据。 第二反馈路径被配置为从第一锁存器接收数据并且向另一个均衡路径的求和节点提供数据。 第二反馈路径提供达到在求和节点之间的数据传播的符号间隔。
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公开(公告)号：US20150016496A1
公开(公告)日：2015-01-15
申请号：US13937925
申请日：2013-07-09
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04L25/03878 , H04L2025/0349 , H04L2025/03617
摘要： A decision feedback equalizer (DFE) circuit includes a first equalization path and a second equalization path. Each equalization path includes a summing node, a first latch, a second latch, a first feedback path, and a second feedback path. The first latch is configured to latch data received from the summing node. The second latch is configured to latch data received from the first latch. The first feedback path is configured to receive data from the second latch and to provide data to the summing node of the equalization path. The second feedback path is configured to receive data from the first latch and to provide data to the summing node of the other equalization path. The second feedback path provides up to a symbol interval for propagation of data between the summing nodes.
摘要翻译： 判决反馈均衡器（DFE）电路包括第一均衡路径和第二均衡路径。 每个均衡路径包括求和节点，第一锁存器，第二锁存器，第一反馈路径和第二反馈路径。 第一锁存器被配置为锁存从求和节点接收到的数据。 第二锁存器被配置为锁存从第一锁存器接收到的数据。 第一反馈路径被配置为从第二锁存器接收数据并且向均衡路径的求和节点提供数据。 第二反馈路径被配置为从第一锁存器接收数据并且向另一个均衡路径的求和节点提供数据。 第二反馈路径提供达到在求和节点之间的数据传播的符号间隔。
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