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公开(公告)号：US11955879B2
公开(公告)日：2024-04-09
申请号：US17137446
申请日：2020-12-30
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Wadeyar , Vikas Lakhanpal , Preetam Charan Anand Tadeparthy
Abstract: In described examples, a controller includes a converter. The converter generates a first signal responsive to an input signal. A summing block is coupled to the converter. The summing block receives the first signal and generates a second signal. A limiter is coupled to the summing block and generates a third signal responsive to the second signal and a code signal. A logic block generates a target signal responsive to the third signal. The third signal transitions to an intermediate level at a first slew rate and the third signal transitions from the intermediate level to the target signal at a second slew rate.
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Patent Agency Ranking
公开(公告)号：US11881774B2
公开(公告)日：2024-01-23
申请号：US17200564
申请日：2021-03-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Bikash Kumar Pradhan , Preetam Charan Anand Tadeparthy , Muthusubramanian Venkateswaran , Venkatesh Wadeyar , Siddaram Mathapathi
CPC classification number: H02M3/158 , H02M1/00 , H02M1/0045
Abstract: A controller includes: a pulse-width modulation (PWM) circuit; a control loop; and a reference voltage controller. The control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a PWM control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the PWM control input. The reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.
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公开(公告)号：US12231045B2
公开(公告)日：2025-02-18
申请号：US18539346
申请日：2023-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Bikash Kumar Pradhan , Preetam Charan Anand Tadeparthy , Muthusubramanian Venkateswaran , Venkatesh Wadeyar , Siddaram Mathapathi
Abstract: A controller includes: a pulse-width modulation (PWM) circuit; a control loop; and a reference voltage controller. The control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a PWM control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the PWM control input. The reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.
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公开(公告)号：US11720159B2
公开(公告)日：2023-08-08
申请号：US16917423
申请日：2020-06-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkatesh Wadeyar , Vikas Lakhanpal , Preetam Charan Anand Tadeparthy
CPC classification number: G06F1/28 , G06F13/4282
Abstract: In described examples, a voltage regulator includes a processor. A register bank is coupled to the processor. A logic block is coupled to the processor and to the register bank. The logic block receives frames. The processor programs the logic block and the register bank based on at least one of the frames.
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公开(公告)号：US20220209648A1
公开(公告)日：2022-06-30
申请号：US17137446
申请日：2020-12-30
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Wadeyar , Vikas Lakhanpal , Preetam Charan Anand Tadeparthy
Abstract: In described examples, a controller includes a converter. The converter generates a first signal responsive to an input signal. A summing block is coupled to the converter. The summing block receives the first signal and generates a second signal. A limiter is coupled to the summing block and generates a third signal responsive to the second signal and a code signal. A logic block generates a target signal responsive to the third signal. The third signal transitions to an intermediate level at a first slew rate and the third signal transitions from the intermediate level to the target signal at a second slew rate.
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公开(公告)号：US20210004072A1
公开(公告)日：2021-01-07
申请号：US16917423
申请日：2020-06-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkatesh Wadeyar , Vikas Lakhanpal , Preetam Charan Anand Tadeparthy
Abstract: In described examples, a voltage regulator includes a processor. A register bank is coupled to the processor. A logic block is coupled to the processor and to the register bank. The logic block receives frames. The processor programs the logic block and the register bank based on at least one of the frames.
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