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    Phase-locked loop slip detector
    1.
    发明授权
    Phase-locked loop slip detector 有权

    公开(公告)号：US11133807B2

    公开(公告)日：2021-09-28

    申请号：US16703232

    申请日：2019-12-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das ,  Jiankun Hu

    IPC: H03L7/089 ,  H03L7/095 ,  H03L7/087

    Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

    Phase-locked loop slip detector
    2.
    发明授权
    Phase-locked loop slip detector 有权

    公开(公告)号：US11444626B2

    公开(公告)日：2022-09-13

    申请号：US17458001

    申请日：2021-08-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das ,  Jiankun Hu

    IPC: H03L7/089 ,  H03L7/095 ,  H03L7/087

    Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

    Phase lock loop reference loss detection
    3.
    发明授权
    Phase lock loop reference loss detection 有权

    公开(公告)号：US11239847B2

    公开(公告)日：2022-02-01

    申请号：US16940880

    申请日：2020-07-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

    IPC: H03L7/087 ,  H03L7/099

    Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

    Phase-locked loop slip detector
    4.
    发明授权
    Phase-locked loop slip detector 有权

    公开(公告)号：US12052021B2

    公开(公告)日：2024-07-30

    申请号：US17931165

    申请日：2022-09-12

    Applicant: Texas Instruments Incorporated

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das ,  Jiankun Hu

    IPC: H03L7/089 ,  H03L7/087 ,  H03L7/095

    CPC classification number: H03L7/0891 ,  H03L7/087 ,  H03L7/095

    Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

    Phase lock loop reference loss detection
    6.
    发明授权
    Phase lock loop reference loss detection 有权

    公开(公告)号：US10727841B2

    公开(公告)日：2020-07-28

    申请号：US16167440

    申请日：2018-10-22

    Applicant: Texas Instruments Incorporated

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

    IPC: H03L7/087 ,  H03L7/099

    Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

    PHASE LOCK LOOP REFERENCE LOSS DETECTION
    8.
    发明申请
    PHASE LOCK LOOP REFERENCE LOSS DETECTION 有权

    公开(公告)号：US20220103181A1

    公开(公告)日：2022-03-31

    申请号：US17550123

    申请日：2021-12-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

    IPC: H03L7/087 ,  H03L7/099

    Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

    PHASE LOCK LOOP REFERENCE LOSS DETECTION
    9.
    发明申请
    PHASE LOCK LOOP REFERENCE LOSS DETECTION 审中-公开

    公开(公告)号：US20200127667A1

    公开(公告)日：2020-04-23

    申请号：US16167440

    申请日：2018-10-22

    Applicant: Texas Instruments Incorporated

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

    IPC: H03L7/087 ,  H03L7/099

    Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

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