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公开(公告)号：US11133807B2
公开(公告)日：2021-09-28
申请号：US16703232
申请日：2019-12-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shailesh Ganapat Ghotgalkar , Wei Fu , Venkatseema Das , Jiankun Hu
Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.
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公开(公告)号：US09252663B2
公开(公告)日：2016-02-02
申请号：US14039661
申请日：2013-09-27
Applicant: Texas Instruments Incorporated
Inventor： Wei Fu , Karan Singh Bhatia , Siang Tong Tan
CPC classification number: H02M3/1563 , G05F1/575 , H02M3/158 , H02M2001/0032 , Y02B70/16
Abstract: An output voltage is compared to a reference voltage, comparison signals are generated, and control signals and mode signals are generated in response thereto. The output voltage is generated in response to the control signals. A speed of the comparing is increased in response to the mode signals indicating that the output voltage is being increased. The speed is reduced in response to the mode signals indicating that the output voltage is being reduced. For increasing the speed, a path is enabled to conduct current. While the path is enabled, at least one switched voltage is connected to vary an amount of the current conducted through the path. The switched voltage is at least one of the reference voltage and the output voltage. For reducing the speed, the path is disabled against conducting current. While the path is disabled, the switched voltage is disconnected from varying the amount.
Abstract translation: 将输出电压与参考电压进行比较，生成比较信号，响应于此产生控制信号和模式信号。 响应于控制信号产生输出电压。 响应于表示输出电压增加的模式信号，比较速度增加。 响应于表示输出电压正在减小的模式信号，速度降低。 为了提高速度，可以通过一个路径来传导电流。 当路径被使能时，连接至少一个开关电压以改变通过路径传导的电流量。 开关电压是参考电压和输出电压中的至少一个。 为了降低速度，路径禁止传导电流。 当路径被禁用时，切换的电压被断开以改变量。
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公开(公告)号：US20150091538A1
公开(公告)日：2015-04-02
申请号：US14039661
申请日：2013-09-27
Applicant: Texas Instruments Incorporated
Inventor： Wei Fu , Karan Singh Bhatia , Siang Tong Tan
IPC: H02M3/158
CPC classification number: H02M3/1563 , G05F1/575 , H02M3/158 , H02M2001/0032 , Y02B70/16
Abstract: An output voltage is compared to a reference voltage, comparison signals are generated, and control signals and mode signals are generated in response thereto. The output voltage is generated in response to the control signals. A speed of the comparing is increased in response to the mode signals indicating that the output voltage is being increased. The speed is reduced in response to the mode signals indicating that the output voltage is being reduced. For increasing the speed, a path is enabled to conduct current. While the path is enabled, at least one switched voltage is connected to vary an amount of the current conducted through the path. The switched voltage is at least one of the reference voltage and the output voltage. For reducing the speed, the path is disabled against conducting current. While the path is disabled, the switched voltage is disconnected from varying the amount.
Abstract translation: 将输出电压与参考电压进行比较，生成比较信号，响应于此产生控制信号和模式信号。 响应于控制信号产生输出电压。 响应于表示输出电压增加的模式信号，比较速度增加。 响应于表示输出电压正在减小的模式信号，速度降低。 为了提高速度，可以通过一个路径来传导电流。 当路径被使能时，连接至少一个开关电压以改变通过路径传导的电流量。 开关电压是参考电压和输出电压中的至少一个。 为了降低速度，路径禁止传导电流。 当路径被禁用时，切换的电压被断开以改变量。
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公开(公告)号：US20250048721A1
公开(公告)日：2025-02-06
申请号：US18228385
申请日：2023-07-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eung Jung Kim , Thomas Grebs , Sunglyong Kim , Sungho Beck , Wei Fu , Xiaochun Zhao , Arjun Pankaj
IPC: H01L29/78 , H01L27/06 , H01L27/092 , H01L29/06 , H01L29/40 , H01L29/66 , H01L29/786
Abstract: Described examples include an integrated circuit having first and second transistors. The first transistor includes a plurality of trenches extending into a semiconductor substrate and a plurality of source regions, each source region located between a pair of adjacent trenches. A first source terminal is connected to the plurality of source regions. The second transistor includes a central source region between a pair of the trenches and a second source terminal connected to the central source region. The second source terminal is conductively isolated from the first source terminal.
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公开(公告)号：US12052021B2
公开(公告)日：2024-07-30
申请号：US17931165
申请日：2022-09-12
Applicant: Texas Instruments Incorporated
Inventor： Shailesh Ganapat Ghotgalkar , Wei Fu , Venkatseema Das , Jiankun Hu
CPC classification number: H03L7/0891 , H03L7/087 , H03L7/095
Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.
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Patent Agency Ranking
公开(公告)号：US11990914B2
公开(公告)日：2024-05-21
申请号：US17550123
申请日：2021-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shailesh Ganapat Ghotgalkar , Wei Fu , Venkatseema Das
Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.
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公开(公告)号：US10784875B2
公开(公告)日：2020-09-22
申请号：US16231568
申请日：2018-12-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Krishnaswamy Nagaraj , Wei Fu
Abstract: A circuit includes a first filter, a plurality of binary-weighted capacitors, and a current source device. The circuit also includes a first plurality of switches. Each of the first plurality of switches is connected to a separate capacitor of the plurality of binary-weighted capacitors. The first plurality of switches are connected together, and the first plurality of switches are not connected to the first filter. A second plurality of switches is also included, and each of the second plurality of switches is connected to a separate capacitor of the plurality of binary-weighted capacitors and to the first filter and to a control input of the current source device. The first plurality of switches are not connected to the control input.
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公开(公告)号：US10727841B2
公开(公告)日：2020-07-28
申请号：US16167440
申请日：2018-10-22
Applicant: Texas Instruments Incorporated
Inventor： Shailesh Ganapat Ghotgalkar , Wei Fu , Venkatseema Das
Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.
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公开(公告)号：US11444626B2
公开(公告)日：2022-09-13
申请号：US17458001
申请日：2021-08-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shailesh Ganapat Ghotgalkar , Wei Fu , Venkatseema Das , Jiankun Hu
Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.
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公开(公告)号：US11239847B2
公开(公告)日：2022-02-01
申请号：US16940880
申请日：2020-07-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shailesh Ganapat Ghotgalkar , Wei Fu , Venkatseema Das
Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.
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