公开(公告)号：US20240112953A1

公开(公告)日：2024-04-04

申请号：US18148231

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Byron Lovell Williams ,  Kashyap Barot ,  Viresh Chinchansure ,  Sreeram N S

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528

Abstract: A microelectronic device including a galvanic isolator with filler metal within an upper isolation element. The galvanic isolator includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The upper isolation element contains tines of filler metal which are electrically tied to each other and are electrically tied to the upper isolation element. The ends of the tines are rounded to minimize electric fields. The filler metal increases the overall metal density on the metal layer of the upper isolation element to meet the typical metal density requirements of modern microelectronic fabrication processing.

公开(公告)号：US20240194583A1

公开(公告)日：2024-06-13

申请号：US18128490

申请日：2023-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kumar Anurag Shrivastava ,  Viresh Chinchansure

IPC: H01L23/522

CPC classification number: H01L23/5223 ,  H01L28/86 ,  H01L28/90

Abstract: An integrated circuit includes first second metal levels over a semiconductor substrate. A first capacitor electrode in the first metal level has a plurality of first lines. A second capacitor electrode in the first metal level includes a plurality of second lines alternating with the plurality of first metal lines. A third capacitor electrode in the second metal level includes a plurality of third lines. And a fourth capacitor electrode in the second metal level includes a plurality of fourth parallel lines alternating with the plurality of third metal lines. Each of the third lines is located over a first one of the first lines and a first one of the second lines, and each of the fourth lines is located over a second one of the first lines and a second one of the second lines.

公开(公告)号：US20240112852A1

公开(公告)日：2024-04-04

申请号：US17957875

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  Kashyap Barot ,  Sreeram N. S. ,  Viresh Chinchansure

IPC: H01F27/32 ,  H01F41/12

CPC classification number: H01F27/324 ,  H01F41/122 ,  H01F2027/329

Abstract: A microelectronic device includes a galvanic isolation component. The galvanic isolation component includes a lower winding and an upper isolation element over the lower winding. The galvanic isolation component further includes a field suppression structure located interior to the lower winding. The field suppression structure includes a conductive field deflector that is separated from the lower winding by a lateral distance that is half a thickness of the lower winding to twice the thickness of the lower winding. A top surface of the conductive field deflector is substantially coplanar with a bottom surface of the lower winding. The conductive field deflector is electrically connected to a semiconductor material in a substrate. The lower winding is separated from a substrate by a first dielectric layer. The upper isolation element is separated from the lower winding by a second dielectric layer.