公开(公告)号：US11075620B2

公开(公告)日：2021-07-27

申请号：US17071803

申请日：2020-10-15

Applicant: Texas Instruments Incorporated

Inventor： Shuing Ju ,  Wenxiao Tan ,  Arun Rao

IPC: H03K4/48

Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.

公开(公告)号：US20180115268A1

公开(公告)日：2018-04-26

申请号：US15331213

申请日：2016-10-21

Applicant: Texas Instruments Incorporated

Inventor： Qunying Li ,  Joao Carlos Felicio Brito ,  Wenxiao Tan

IPC: H02P25/034 ,  H02P7/03

CPC classification number: H02P25/034 ,  H02P7/04

Abstract: Methods and apparatus providing a smooth transition from a pulse width modulation mode to a linear mode to drive a voice coil motor are disclosed. An example apparatus includes an H-bridge; a pulse generator to generate a pulse when the voice coil motor driver transitions from pulse width modulation mode to linear mode; a first boost circuit to, when the pulse is generated, increase a first current being applied to a first gate of a first transistor in the H-bridge, the increase in the first current enabling the first transistor; and a second boost circuit to, when the pulse is generated, provide an additional path to ground from a node coupled to a second gate of a second transistor of the H bridge, the path to ground corresponding to a voltage drop that disables the second transistor.

公开(公告)号：US08975964B2

公开(公告)日：2015-03-10

申请号：US13759848

申请日：2013-02-05

Applicant: Texas Instruments Incorporated

Inventor： Qunying Li ,  Wenxiao Tan ,  Gregory Swize

IPC: H03G3/00 ,  H03G1/00

CPC classification number: H03G3/00 ,  H03G1/0088 ,  H03G3/001

Abstract: A high performance digitalized Programmable Gain Amplifier (PGA). In prior art circuit, a dual-ladder DAC is employed for gain control, the back gate leakage of NMOS resistors in the fine ladder conquers fine ladder nominal current and it produces non-monotonic gain scallop. Two new art design techniques: (1) adaptively control the fine ladder; and (2) use dummy PMOS brunch device leakage compensates for the NMOS resistor device leakage, are proposed so that the non-monotonic scallops are substantially eliminated and 13-bit resolution/accuracy PGA has been achieved.

Abstract translation: 高性能数字化可编程增益放大器（PGA）。 在现有技术的电路中，采用双梯形DAC进行增益控制，精细梯形图中的NMOS电阻的背栅极泄漏征服了细梯级标称电流，并产生非单调增益扇贝。 两种新的艺术设计技巧：（1）适应性地控制细梯; 并且（2）使用虚拟PMOS快速装置漏电补偿NMOS电阻器件泄漏，从而基本上消除了非单调扇贝，并且已经实现了13位分辨率/精度PGA。

公开(公告)号：US10547267B2

公开(公告)日：2020-01-28

申请号：US15331213

申请日：2016-10-21

Applicant: Texas Instruments Incorporated

Inventor： Qunying Li ,  Joao Carlos Felicio Brito ,  Wenxiao Tan

IPC: H02P7/00 ,  H02P25/034 ,  H02P7/03

Abstract: Methods and apparatus providing a smooth transition from a pulse width modulation mode to a linear mode to drive a voice coil motor are disclosed. An example apparatus includes an H-bridge; a pulse generator to generate a pulse when the voice coil motor driver transitions from pulse width modulation mode to linear mode; a first boost circuit to, when the pulse is generated, increase a first current being applied to a first gate of a first transistor in the H-bridge, the increase in the first current enabling the first transistor; and a second boost circuit to, when the pulse is generated, provide an additional path to ground from a node coupled to a second gate of a second transistor of the H bridge, the path to ground corresponding to a voltage drop that disables the second transistor.

公开(公告)号：US10530308B2

公开(公告)日：2020-01-07

申请号：US15934467

申请日：2018-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shyamsunder Balasubramanian ,  Wenxiao Tan ,  Mayank Garg ,  Toru Tanaka

IPC: H03F3/04 ,  H03F1/30

Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.

公开(公告)号：US20210028775A1

公开(公告)日：2021-01-28

申请号：US17071803

申请日：2020-10-15

Applicant: Texas Instruments Incorporated

Inventor： Shuing Ju ,  Wenxiao Tan ,  Arun Rao

IPC: H03K4/48

Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.

公开(公告)号：US10855263B2

公开(公告)日：2020-12-01

申请号：US16428345

申请日：2019-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shuing Ju ,  Wenxiao Tan ,  Arun Rao

IPC: H03K4/48

Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.

公开(公告)号：US10027295B2

公开(公告)日：2018-07-17

申请号：US15142134

申请日：2016-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wenxiao Tan ,  Mayank Garg ,  Noble Narku-Tetteh

IPC: H02P1/00 ,  H03F3/45 ,  H03F1/56 ,  H02P31/00 ,  G11C7/06

Abstract: An electrical device (e.g., an integrated circuit) includes an amplifier, a configurable common mode gain trim circuit, and a memory. The configurable common mode gain trim circuit is coupled to the amplifier. The memory is configured to include trim data that is usable during an initialization process for the electrical device to configure the impedance matching circuit.

公开(公告)号：US20130200954A1

公开(公告)日：2013-08-08

申请号：US13759848

申请日：2013-02-05

Applicant: Texas Instruments Incorporated

Inventor： Qunying Li ,  Wenxiao Tan ,  Gregory Swize

IPC: H03G3/00

CPC classification number: H03G3/00 ,  H03G1/0088 ,  H03G3/001

Abstract: A high performance digitalized Programmable Gain Amplifier (PGA). In prior art circuit, a dual-ladder DAC is employed for gain control, the back gate leakage of NMOS resistors in the fine ladder conquers fine ladder nominal current and it produces non-monotonic gain scallop. Two new art design techniques: (1) adaptively control the fine ladder; and (2) use dummy PMOS brunch device leakage compensates for the NMOS resistor device leakage, are proposed so that the non-monotonic scallops are substantially eliminated and 13-bit resolution/accuracy PGA has been achieved.

Abstract translation: 高性能数字化可编程增益放大器（PGA）。 在现有技术的电路中，采用双梯形DAC进行增益控制，精细梯形图中的NMOS电阻的背栅极泄漏征服了细梯级标称电流，并产生非单调增益扇贝。 两种新的艺术设计技巧：（1）适应性地控制细梯; 并且（2）使用虚拟PMOS快速装置漏电补偿NMOS电阻器件泄漏，从而基本上消除了非单调扇贝，并且已经实现了13位分辨率/精度PGA。