公开(公告)号：US12003229B2

公开(公告)日：2024-06-04

申请号：US17348521

申请日：2021-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Cetin Kaya ,  Nathan Richard Schemm ,  Yong Xie

IPC: H02H7/00 ,  G01K7/02 ,  G01R1/20 ,  G01R19/165 ,  G05F1/46 ,  H03K5/24 ,  H03K17/082

CPC classification number: H03K17/0822 ,  G01K7/02 ,  G01R1/203 ,  G01R19/16538 ,  G05F1/461 ,  H03K5/24

Abstract: A short circuit detection circuit includes a current terminal, a sense resistor, an amplifier, and a resistor-capacitor ladder. The sense resistor is coupled to the current terminal, and is configured to develop a sense voltage proportional to a current through the current terminal. The amplifier is coupled to the sense resistor, and is configured to generate a scaled current proportional to the sense voltage. The resistor-capacitor ladder is coupled to the amplifier, and is configured to generate a measurement voltage that represents a surface temperature rise due to the current through the current terminal.

公开(公告)号：US20240275374A1

公开(公告)日：2024-08-15

申请号：US18645774

申请日：2024-04-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Cetin Kaya ,  Nathan Richard Schemm ,  Yong Xie

IPC: H03K17/082 ,  G01K7/02 ,  G01R1/20 ,  G01R19/165 ,  G05F1/46 ,  H03K5/24

CPC classification number: H03K17/0822 ,  G01K7/02 ,  G01R1/203 ,  G01R19/16538 ,  G05F1/461 ,  H03K5/24

Abstract: A short circuit detection circuit includes a current terminal, a sense resistor, an amplifier, and a resistor-capacitor ladder. The sense resistor is coupled to the current terminal, and is configured to develop a sense voltage proportional to a current through the current terminal. The amplifier is coupled to the sense resistor, and is configured to generate a scaled current proportional to the sense voltage. The resistor-capacitor ladder is coupled to the amplifier, and is configured to generate a measurement voltage that represents a surface temperature rise due to the current through the current terminal.

公开(公告)号：US20210297075A1

公开(公告)日：2021-09-23

申请号：US17322018

申请日：2021-05-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yong Xie ,  Michael Lüeders ,  Cetin Kaya

IPC: H03K17/284 ,  H02M1/08 ,  G05F1/56

Abstract: Methods, apparatus, and systems are disclosed to drive a transistor. An example apparatus includes a regulator including a first input terminal adapted to be coupled to a control terminal of a transistor, a first output terminal, and a second output terminal, a first stage including a first input terminal coupled to the first output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor, and a second stage including an input terminal coupled to the second output terminal of the regulator, and an output terminal adapted to be coupled to the control terminal of the transistor.

公开(公告)号：US11038502B1

公开(公告)日：2021-06-15

申请号：US16827357

申请日：2020-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yong Xie ,  Michael Lüeders ,  Cetin Kaya

IPC: H03K3/00 ,  H03K17/284 ,  H02M1/08 ,  G05F1/56

Abstract: Methods, apparatus, and systems are disclosed to drive a transistor. An example apparatus includes a regulator including a first input terminal adapted to be coupled to a control terminal of a transistor, a first output terminal, and a second output terminal, a first stage including a first input terminal coupled to the first output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor, and a second stage including an input terminal coupled to the second output terminal of the regulator, and an output terminal adapted to be coupled to the control terminal of the transistor.

公开(公告)号：US20210175195A1

公开(公告)日：2021-06-10

申请号：US17028353

申请日：2020-09-22

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yong Xie ,  Rajen Manicon Murugan ,  Woochan Kim

IPC: H01L23/00 ,  H01L25/16

Abstract: In described examples of a circuit module, a multilayer substrate has a conductive pad formed on a surface of the multilayer substrate. An integrated circuit (IC) die is bonded to the surface of the substrate in dead bug manner, such that a set of bond pads formed on a surface of the IC die are exposed. A planar interconnect line formed by printed ink couples the set of bond pads to the conductive pad.