公开(公告)号：US20140189256A1

公开(公告)日：2014-07-03

申请号：US13729718

申请日：2012-12-28

申请人： TIM KRANICH ,  GILLES A. POKAM ,  JUSTIN E. GOTTSCHLICH ,  KLAUS DANNE ,  ROLF KASSA ,  SHILIANG HU ,  CRISTIANO L. PEREIRA

发明人： TIM KRANICH ,  GILLES A. POKAM ,  JUSTIN E. GOTTSCHLICH ,  KLAUS DANNE ,  ROLF KASSA ,  SHILIANG HU ,  CRISTIANO L. PEREIRA

IPC分类号： G06F12/08

CPC分类号： G06F9/526 ,  G06F11/3404 ,  G06F11/3409 ,  G06F11/3471 ,  G06F11/36 ,  G06F11/3636

摘要： A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.

摘要翻译： 处理器包括执行第一软件线程的第一核，执行第二软件线程的第二核和共享存储器存取监视和记录逻辑。 该逻辑包括存储器访问监视器逻辑，以监视第一线程对存储器的访问，记录被监视的访问的存储器地址，以及检测与其他线程相关的记录存储器地址的数据比赛。 逻辑包括块生成逻辑是生成块来表示第一个线程的提交执行。 每个块都包括执行和提交的第一个线程的一些指令和一个时间戳。 块生成逻辑是通过存储器访问监视器逻辑来检测数据竞赛来停止生成当前块。 块缓冲区是临时存储块，直到块被从处理器传出。

公开(公告)号：US20160266901A1

公开(公告)日：2016-09-15

申请号：US14643855

申请日：2015-03-10

申请人： SEBASTIAN WINKEL ,  GIRISH VENKATASUBRAMANIAN ,  TYLER N. SONDAG ,  ROLF KASSA

发明人： SEBASTIAN WINKEL ,  GIRISH VENKATASUBRAMANIAN ,  TYLER N. SONDAG ,  ROLF KASSA

IPC分类号： G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/30145 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863

摘要： A method and apparatus are described for efficient register reclamation. For example, one embodiment of an apparatus comprises: single usage detection and tagging logic to examine a sequence of instructions to detect logical registers used by the sequence of instructions that have a single use and to tag an instruction as a single usage instruction if the instruction is a consumer of a logical register that has a single use; an allocator to allocate processor resources to execute the sequence of instructions, the processor resources including physical registers mapped to logical registers to execute the sequence of instructions; and register reclamation logic to free up a logical to physical mapping of a single use register in response to detecting the tag provided by the instruction tagging logic.

摘要翻译： 描述了用于有效的寄存器回收的方法和装置。 例如，设备的一个实施例包括：单次使用检测和标记逻辑，用于检查指令序列，以检测由具有一次使用的指令序列使用的逻辑寄存器，并且如果指令是将指令标记为单个使用指令 是具有单次使用的逻辑寄存器的消费者; 分配器，用于分配处理器资源来执行所述指令序列，所述处理器资源包括映射到逻辑寄存器的物理寄存器，以执行所述指令序列; 并且响应于检测到由指令标记逻辑提供的标签来注册回收逻辑以释放单个使用寄存器的逻辑到物理映射。