公开(公告)号：US11830852B2

公开(公告)日：2023-11-28

申请号：US17541581

申请日：2021-12-03

Applicant: TOKYO ELECTRON LIMITED

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin ,  Brian Cline ,  Xiaoqing Xu ,  David Pietromonaco

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L23/5286 ,  H01L25/18 ,  H01L2225/06544

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.

公开(公告)号：US12224281B2

公开(公告)日：2025-02-11

申请号：US17541609

申请日：2021-12-03

Applicant: TOKYO ELECTRON LIMITED

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin ,  Brian Cline ,  Xiaoqing Xu ,  David Pietromonaco

IPC: H01L27/06 ,  H01L27/092

Abstract: A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.

公开(公告)号：US12176293B2

公开(公告)日：2024-12-24

申请号：US17541561

申请日：2021-12-03

Applicant: TOKYO ELECTRON LIMITED

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin ,  Brian Cline ,  Xiaoqing Xu ,  David Pietromonaco

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a lower semiconductor device tier, and a lower signal wiring structure electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include an upper semiconductor device tier disposed over and electrically connected the first PDN structure, and an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier.