公开(公告)号：US20180082464A1

公开(公告)日：2018-03-22

申请号：US15268495

申请日：2016-09-16

申请人： TOMAS G. AKENINE-MOLLER ,  ROBERT M. TOTH ,  BRENT E. INSKO ,  PETER L. DOYLE ,  PRASOONKUMAR SURTI ,  MAIYURAN SUBRAMANIAM ,  CARL JACOB MUNKBERG ,  FRANZ PETRIK CLARBERG ,  JON N. HASSELGREN

发明人： TOMAS G. AKENINE-MOLLER ,  ROBERT M. TOTH ,  BRENT E. INSKO ,  PETER L. DOYLE ,  PRASOONKUMAR SURTI ,  MAIYURAN SUBRAMANIAM ,  CARL JACOB MUNKBERG ,  FRANZ PETRIK CLARBERG ,  JON N. HASSELGREN

IPC分类号： G06T15/00 ,  G06T17/10 ,  G06T15/80 ,  G06T15/30 ,  G06T15/40 ,  G06T17/20 ,  G06T15/04 ,  G06T15/20

CPC分类号： G06T15/005 ,  G06T15/04 ,  G06T15/205 ,  G06T15/30 ,  G06T15/405 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20 ,  G06T2210/12

摘要： A graphics processing apparatus and method are described. For example, one embodiment of a graphics processing apparatus comprises: an input assembler of a graphics pipeline to determine a first set of triangles to be drawn based on application-provided parameters; a depth buffer to store depth data related to the first set of triangles; a vertex shader to perform position-only vertex shading operations on the first set of triangles in response to an indication that the graphics pipeline is to initially operate in a depth-only mode; a culling and clipping module to read depth values from the depth buffer to identify those triangles in the first set of triangles which are fully occluded by other objects in a current frame and to generate culling data usable to cull occluded triangles, the culling and clipping module to associate the culling data with a replay token to be used to identify a subsequent rendering pass through the graphics pipeline; the input assembler, upon detecting the replay token in the subsequent rendering pass, to access the culling data associated therewith to remove culled triangles from the first set of triangles to generate a second set of triangles; the vertex shader to perform full vertex shading operations on the second set of triangles during the subsequent rendering pass, the replay token to be destroyed during or following the subsequent rendering pass.

公开(公告)号：US20180082465A1

公开(公告)日：2018-03-22

申请号：US15268496

申请日：2016-09-16

申请人： PRASOONKUMAR SURTI ,  TOMAS G. AKENINE-MOLLER ,  DAVID COWPERTHWAITE ,  KEVIN TIAN ,  PETER L. DOYLE ,  BRENT INSKO ,  ADAM T. LAKE

发明人： PRASOONKUMAR SURTI ,  TOMAS G. AKENINE-MOLLER ,  DAVID COWPERTHWAITE ,  KEVIN TIAN ,  PETER L. DOYLE ,  BRENT INSKO ,  ADAM T. LAKE

IPC分类号： G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06T15/40 ,  G06T15/50

CPC分类号： G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T15/405 ,  G06T15/503 ,  G06T2207/20021 ,  G06T2210/12

摘要： A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

公开(公告)号：US20180292897A1

公开(公告)日：2018-10-11

申请号：US15482694

申请日：2017-04-07

申请人： INGO WALD ,  BRENT E. INSKO ,  PRASOONKUMAR SURTI ,  KUN TIAN ,  ADAM T. LAKE ,  YAO ZU EDDIE DONG ,  PETER L. DOYLE

发明人： INGO WALD ,  BRENT E. INSKO ,  PRASOONKUMAR SURTI ,  KUN TIAN ,  ADAM T. LAKE ,  YAO ZU EDDIE DONG ,  PETER L. DOYLE

IPC分类号： G06F3/01 ,  G06T15/80 ,  G06T15/04 ,  G06T15/06

摘要： One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

公开(公告)号：US20140085302A1

公开(公告)日：2014-03-27

申请号：US13627699

申请日：2012-09-26

申请人： PETER L. DOYLE ,  THOMAS A. PIAZZA

发明人： PETER L. DOYLE ,  THOMAS A. PIAZZA

IPC分类号： G06T17/10

CPC分类号： G06T1/60 ,  G06T15/005 ,  G06T17/20

摘要： An apparatus may include a memory to store a set of triangle vertices in a triangle, a processor circuit coupled to the memory and a cache to cache a set of triangle vertex indices corresponding to triangle vertices most recently transmitted through a graphics pipeline. The apparatus may also include an autostrip vertex processing component operative on the processor circuit to receive from the memory the set of triangle vertices, compare an index for each vertex of the set of triangle vertices to determine matches to the set of cached triangle vertex indices, and shift a single vertex index into the cache, the single vertex index corresponding to a vertex miss in which a given vertex of the set of triangle vertices does not match any vertex index of the set of cached triangle vertex indices when exactly two matches to the set of cached triangle vertex indices are found.

摘要翻译： 装置可以包括存储器，用于存储三角形中的一组三角形顶点，耦合到存储器的处理器电路和高速缓存，以缓存对应于最近通过图形管线传输的三角形顶点的一组三角形顶点索引。 该装置还可以包括在处理器电路上操作以从存储器接收该组三角形顶点的自动条带顶点处理组件，比较该组三角形顶点的每个顶点的索引，以确定与该组缓存的三角形顶点索引的匹配， 并将单个顶点索引移动到高速缓存中，对应于顶点未​​命中的单个顶点索引，其中三角形顶点集合的给定顶点与该组高速缓存的三角形顶点索引的任何顶点索引不匹配，当恰好两个匹配时 找到一组缓存的三角形顶点索引。

公开(公告)号：US20150379664A1

公开(公告)日：2015-12-31

申请号：US14316895

申请日：2014-06-27

申请人： KALYAN K. BHIRAVABHATLA ,  PETER L. DOYLE ,  SUBRAMANIAM MAIYURAN

发明人： KALYAN K. BHIRAVABHATLA ,  PETER L. DOYLE ,  SUBRAMANIAM MAIYURAN

IPC分类号： G06T1/20 ,  G06T17/10

CPC分类号： G06T15/30

摘要： Methods and hardware may process single plane clipping operations using a pipeline specialized for single plane clipping. A second pipeline may be provided to handle clipping in multi-clipping plane cases. By optimizing the hardware and methods around single plane clipping, polygon throughput may be enhanced.

摘要翻译： 方法和硬件可以使用专用于单平面限幅的流水线处理单平面剪切操作。 可以提供第二管线来处理多裁剪平面情况下的削波。 通过优化围绕单平面剪切的硬件和方法，可以增强多边形吞吐量。

公开(公告)号：US20190066354A1

公开(公告)日：2019-02-28

申请号：US15692951

申请日：2017-08-31

申请人： HEMA C. NALLURI ,  BALAJI VEMBU ,  PETER L. DOYLE ,  MICHAEL APODACA ,  JEFFERY S. BOLES

发明人： HEMA C. NALLURI ,  BALAJI VEMBU ,  PETER L. DOYLE ,  MICHAEL APODACA ,  JEFFERY S. BOLES

IPC分类号： G06T15/00 ,  G06T17/10 ,  G06T7/507 ,  G06T15/30 ,  G06T1/60

摘要： An apparatus and method are described for culling commands in a tile-based renderer. For example, one embodiment of an apparatus comprises: a command buffer to store a plurality of commands to be executed by a render pipeline to render a plurality of tiles; visibility analysis circuitry to determine per-tile visibility information for each of the plurality of tiles and to store the visibility information for a first tile in a first storage, the visibility information specifying either that all of the commands associated with rendering the first tile can be skipped or identifying individual commands associated with rendering the first tile that can be skipped; and a render pipeline to read the visibility information from the first storage to determine whether to execute or skip one or more of the commands from the command buffer to render the first tile.

公开(公告)号：US20160093102A1

公开(公告)日：2016-03-31

申请号：US14495926

申请日：2014-09-25

申请人： PETER L. DOYLE

发明人： PETER L. DOYLE

IPC分类号： G06T17/20 ,  G06T1/20 ,  G06T1/60 ,  G06T15/80

CPC分类号： G06T17/20 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

摘要： Systems and methods may provide for conducting a region determination of whether one or more domain points associated with a tessellated patch are shared between multiple region sets of the tessellated patch. If the one or more domain points are not shared between multiple region sets of the tessellated patch, an intra-region cache may be automatically interrogated for non-shared shading data. If the one or more domain points are shared between multiple region sets of the tessellated patch, an inter-region cache may be automatically interrogated for shared shading data. In one example, one or more references to the shared shading data is generated and associated with the one or more domain points when cache hits occur in the inter-region cache.

摘要翻译： 系统和方法可以提供区域确定与镶嵌补丁相关联的一个或多个域点是否在镶嵌补丁的多个区域集合之间共享。 如果一个或多个域点在分块补丁的多个区域集之间不共享，则区域内高速缓存可以被自动询问用于非共享着色数据。 如果一个或多个域点在镶嵌补丁的多个区域集合之间共享，则可以自动询问区域间高速缓存以用于共享着色数据。 在一个示例中，当在区域间高速缓存中出现高速缓存命中时，生成对共享着色数据的一个或多个引用并与一个或多个域点相关联。