公开(公告)号：US06269385B1

公开(公告)日：2001-07-31

申请号：US09126441

申请日：1998-07-30

申请人： Tack Don Han ,  Woo Chan Park

发明人： Tack Don Han ,  Woo Chan Park

IPC分类号： G06F738

CPC分类号： G06F7/4876 ,  G06F7/49957

摘要： An apparatus and a method for performing rounding and addition in parallel in a floating point multiplier are disclosed, in which operation time and the size of a chip can be reduced. The apparatus includes an adder having an n bit half adder and an 1 bit full adder to add high n+1 bit from carry C and sum S of 2n bit and 1 bit of predictor, a Cinn−2 generator for generating carry Cinn−2 for addition of low n−2 bit to carry C and sum S of 2n bit, a predictor for providing 0 or 1 to the full adder when generating the added carry C of n bit and sum S of n+1 bit, a carry select adder for adding 0 or 1 to high n bit value of carry and sum added through the adder to output its result values i0 and i1, a selector for outputting a control signal of 0 or 1 to select a value obtained by addition and rounding from two output values of the carry select adder, a multiplexer for multiplexing the results of i0 and i1 from one of a round-to-nearest mode, a round-to-zero mode, and a round-to-infinity mode in response to the control signal of the selector, and a qNS0 logic circuit for generating the least significant bit LSB for a round value during no shift (NS). The floating point multiplier supports four rounding modes according to IEEE's standard.

摘要翻译： 公开了一种用于在浮点乘法器中并行执行舍入和加法的装置和方法，其中可以减少操作时间和芯片的尺寸。 该装置包括具有n位半加法器和1位全加器的加法器，用于从进位C加上高n + 1位，并将2n位和1位预测器的和S相加，用于产生进位Cinn-2的Cinn-2发生器 为了加载低n-2位来携带C和2n位的和S，预测器在产生n位的相加进位C和n + 1位的和S时向全加器提供0或1，进位选择 加法器，用于将0或1加到通过加法器相加的进位和加法的高n位值，以输出其结果值i0和i1;输出0或1的控制信号的选择器，以选择通过加法和舍入从2获得的值 进位选择加法器的输出值，用于响应于该控制将多路复用从循环到最近模式，圆到零模式和圆到无限模式之一的i0和i1的结果的多路复用器 信号，以及qNS0逻辑电路，用于在无移位（NS）期间产生一个回合值的最低有效位LSB。 浮点乘法器根据IEEE标准支持四种四舍五入模式。

公开(公告)号：US06791558B2

公开(公告)日：2004-09-14

申请号：US09920209

申请日：2001-08-01

申请人： Woo Chan Park ,  Tack Don Han ,  Il San Kim ,  Kil Whan Lee ,  Sung Bong Yang

发明人： Woo Chan Park ,  Tack Don Han ,  Il San Kim ,  Kil Whan Lee ,  Sung Bong Yang

IPC分类号： G09G536

CPC分类号： G06T15/40

摘要： A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.

摘要翻译： 公开了一种在3D渲染处理器中处理像素光栅化的方法和装置。 根据该方法和装置，在执行纹理映射之前执行主深度检查，从而可以消除纹理映射的不必要的执行。 此外，使用标志存储器可以简单且容易地解决一致性问题，并且通过执行深度读取和深度检查两次，提高了像素高速缓冲存储器的命中率。 因此，该方法和装置在成本，性能和功耗方面是有效的。

公开(公告)号：US06785701B2

公开(公告)日：2004-08-31

申请号：US09841708

申请日：2001-04-23

申请人： Woo Chan Park ,  Tack Don Han

发明人： Woo Chan Park ,  Tack Don Han

IPC分类号： G06F738

CPC分类号： G06F7/485 ,  G06F7/49957 ,  G06F2207/3884

摘要： A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.

摘要翻译： 在同时舍入方法（SRM）型浮点加法器中并行执行IEEE舍入和相加的浮点ALU。 浮点ALU包括用于旁路或反转第一分数部分和第二分数部分的对准/归一化部分，通过执行从指数部分获得的值或通过左侧执行归一化执行右移，执行对准 通过计算相对于第一分数部分的前导零，并获得保护位（G），圆比特（R）和粘性比特（Sy）; 以及相对于通过对准/归一化部输出的第一分数部分和第二分数部分进行加法和舍入的加法和舍入操作部分。 根据浮点ALU，可以减少处理时间和硬件尺寸，可以直接使用SRM的硬件。

公开(公告)号：US06570565B1

公开(公告)日：2003-05-27

申请号：US09630650

申请日：2000-08-02

申请人： Woo Chan Park ,  Tack Don Han

发明人： Woo Chan Park ,  Tack Don Han

IPC分类号： G06T1540

CPC分类号： G06T15/005 ,  G06T15/40

摘要： A 3D graphic accelerator and a method for processing a graphic acceleration using the same is provided in which the inputted primitives are geometrically processed, and existence of any transparent primitives or dominance/rarity of opaque primitives is determined among the geometrically processed primitives. The primitives are rendered in an object-order style and an image-order style in accordance with the determination. The information on the rendered primitives is stored in a corresponding frame buffer and a bucket, and the rendered primitives are display-refreshed. Thus, the 3D graphic accelerator with order- independent transparency and high performance is obtained.

摘要翻译： 提供了3D图形加速器和使用其的图形加速处理方法，其中输入的图元被几何处理，并且在几何处理的图元中确定了不透明图元的任何透明图元或优势/稀有性的存在。 根据确定，原语以对象顺序样式和图像顺序样式呈现。 关于渲染的图元的信息存储在相应的帧缓冲器和桶中，并且渲染的图元被显示刷新。 因此，获得了具有独立于订单的透明度和高性能的3D图形加速器。

公开(公告)号：US07194499B2

公开(公告)日：2007-03-20

申请号：US10231566

申请日：2002-08-30

申请人： Woong Jeong ,  Jong Chul Jeong ,  Woo Chan Park ,  Moon Key Lee ,  Tack Don Han

发明人： Woong Jeong ,  Jong Chul Jeong ,  Woo Chan Park ,  Moon Key Lee ,  Tack Don Han

IPC分类号： G06F7/52

CPC分类号： G06F7/535 ,  G06F2207/5354

摘要： A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterative operation type. The pipelined divider has a delay time of 3 cycles in a single precision, and can reduce a chip size by about ⅓ in comparison to the existing pipelined divider.

摘要翻译： 公开了具有小查找表的流水线分配器。 流水线分配器可以以低成本大大减小查找表的大小，以克服由于其迭代操作类型而需要大的查找表的传统流水线分配器中涉及的问题。 流水线分配器具有单个精度的3个周期的延迟时间，与现有的流水线分配器相比，可以将芯片尺寸减小约1/3。

公开(公告)号：US06839060B1

公开(公告)日：2005-01-04

申请号：US09650781

申请日：2000-08-30

申请人： Woo Chan Park ,  Tack Don Han

发明人： Woo Chan Park ,  Tack Don Han

IPC分类号： G06T17/00 ,  G06F15/80 ,  G06T1/60 ,  G06T15/00 ,  G06T15/40

CPC分类号： G06T15/00 ,  G06T1/60 ,  G06T15/40 ,  G06T2210/52

摘要： A method and a device of consistency buffer for a high performance 3D graphic accelerator is disclosed to retain consistency without detecting any overlapping region in advance but determining an overlapping with respect to a rendered pixel. The device of consistency buffer according to the present invention comprises a fetch section for transmitting a plurality of primitives to be processed to a vacant region of the buffer, an issue section for buffering the plurality of the primitives transmitted from the said fetch section, and allotting positions to be inputted, a plurality of rendering accelerators for receiving and rendering the plurality of primitives allotted by the issue section, a consistency buffer for storing information required for processing with consistency according to a depth value and a color value of each primitive computed by each of the rendering accelerators, and a memory interface unit for performing read/write computation in a memory by mens of processing with consistency in order based on the information stored in the consistency buffer.

摘要翻译： 公开了一种用于高性能3D图形加速器的一致性缓冲器的方法和装置，以保持一致性，而不事先检测任何重叠区域，但是确定相对于渲染像素的重叠。 根据本发明的一致性缓冲器的装置包括用于将要处理的多个图元发送到缓冲器的空闲区域的提取部分，用于缓冲从所述获取部分发送的多个图元的发行部分，以及分配 要输入的位置，用于接收和呈现由发行部分分配的多个基元的多个渲染加速器，用于根据深度值和每个基本计算的每个图元的颜色值来存储一致性的处理所需的信息的一致性缓冲器 的存储器接口单元，以及存储器接口单元，用于基于存储在一致性缓冲器中的信息，以一致的顺序，通过多项处理在存储器中进行读/写计算。

公开(公告)号：US09311739B2

公开(公告)日：2016-04-12

申请号：US13375112

申请日：2010-05-19

申请人： Jin Suk Hur ,  Woo Chan Park

发明人： Jin Suk Hur ,  Woo Chan Park

IPC分类号： G06T15/06 ,  G06T15/00

CPC分类号： G06T15/06 ,  G06T15/005

摘要： A ray tracing core comprising a ray generation unit and a plurality of T&I (Traversal & Intersection) units with MIMD (Multiple Instruction stream Multiple Data stream) architecture is disclosed. The ray generation unit generates at least one eye ray based on an eye ray generation information. The eye ray generation information includes a screen coordinate value. Each of the plurality of T&I units receives the at least one eye ray and checks whether there exists a triangle intersected with the received at least one eye ray. The triangle configures a space.

摘要翻译： 公开了一种包括具有MIMD（多指令流多数据流）架构的射线产生单元和多个T＆I（穿越和交叉）单元的射线跟踪核心。 射线产生单元基于眼睛线生成信息生成至少一个眼睛射线。 眼线产生信息包括屏幕坐标值。 多个T＆I单元中的每一个接收至少一个眼睛射线并检查是否存在与所接收的至少一个眼睛相交的三角形。 三角形配置一个空格。

公开(公告)号：US08836702B2

公开(公告)日：2014-09-16

申请号：US13985125

申请日：2011-02-18

申请人： Hyung Min Yoon ,  Woo Chan Park

发明人： Hyung Min Yoon ,  Woo Chan Park

IPC分类号： G06T15/30 ,  G06T15/06

CPC分类号： G06T15/06 ,  G06T2200/28

摘要： A ray tracing core comprises a ray tracing unit (RTU), a control unit, and a tree build unit (TBU). The ray tracing unit performs ray tracing based on a spatial partitioning structure. The control unit calculates the degree of complexity of the spatial partitioning structure by monitoring the load state of the ray tracing unit. The tree build unit builds the spatial partitioning structure having the degree of complexity which is calculated. The load state is determined based on a frame rate which is processed in the pertinent unit. The spatial partitioning structure applies a K-dimensional tree. For example, the degree of complexity can be modified according to either the maximum primitive number of a leaf node with respect to a K-dimensional tree structure or a tree depth.

摘要翻译： 光线跟踪核心包括光线跟踪单元（RTU），控制单元和树构建单元（TBU）。 光线跟踪单元基于空间分割结构执行光线跟踪。 控制单元通过监视光线跟踪单元的负载状态来计算空间分割结构的复杂程度。 树构建单元构建具有计算复杂程度的空间分区结构。 基于在相关单元中处理的帧速率来确定负载状态。 空间分割结构应用K维树。 例如，可以根据相对于K维树结构或树深度的叶节点的最大原始数来修改复杂度。

公开(公告)号：US20120044149A1

公开(公告)日：2012-02-23

申请号：US13213926

申请日：2011-08-19

申请人： Dong Kyun Son ,  Dong Han Kang ,  Woo Chan Park ,  Jong Soo Woo ,  Sang Hoon Kang

发明人： Dong Kyun Son ,  Dong Han Kang ,  Woo Chan Park ,  Jong Soo Woo ,  Sang Hoon Kang

IPC分类号： G06F3/023

CPC分类号： G06F3/023

摘要： A misinput avoidance method of a mobile terminal may be implemented to prevent a misinput caused by contacting unintended keys around the target key. A misinput avoidance method of a mobile terminal according to the present invention includes detecting inputs of a plurality of keys and discriminating a target key from other keys. The method also includes extracting keys around the target key and registering the keys around the target keys as neighbor keys. The method further includes processing the input of the target key while blocking the inputs of the neighbor keys. The method further includes releasing, when the target key is released, the blocking of the inputs of the neighbor keys.

摘要翻译： 可以实现移动终端的误输入回避方法，以防止由于围绕目标密钥接触意外的密钥造成的误输。 根据本发明的移动终端的误输入回避方法包括检测多个密钥的输入并且将目标密钥与其他密钥相区别。 该方法还包括提取围绕目标密钥的密钥并将目标密钥周围的密钥注册为相邻密钥。 该方法还包括处理目标密钥的输入，同时阻挡相邻密钥的输入。 该方法还包括当目标密钥被释放时释放邻居密钥的输入的阻塞。

公开(公告)号：US08855582B2

公开(公告)日：2014-10-07

申请号：US11947476

申请日：2007-11-29

申请人： Sang Uk Seo ,  Woo Chan Park

发明人： Sang Uk Seo ,  Woo Chan Park

IPC分类号： H04B1/38 ,  H04M1/656 ,  H04M1/57 ,  H04W4/10 ,  H04W76/00

CPC分类号： H04W4/10 ,  H04M1/575 ,  H04M1/656 ,  H04M1/72519 ,  H04M3/42042 ,  H04M3/533 ,  H04M15/856 ,  H04M2250/60 ,  H04W76/45

摘要： The present invention relates to a mobile communication terminal for Push To Talk (PTT) and a method for processing missed call information thereof, which allows a receiver to check why an originator requested the PTT telephone call during the absence of the receiver through missed call information. The missed call information includes the voice of the originator requesting the PTT call, and the voice of the originator is output when confirmation of the missed call information is requested.

摘要翻译： 本发明涉及一种用于一键通（PTT）的移动通信终端和一种用于处理其未接来电信息的方法，该方法允许接收机通过未接来电信息来检查发信者在接收机不存在期间是否请求PTT电话呼叫的原因 。 未接来电信息包括请求PTT呼叫的发起者的语音，并且在请求确认未接呼叫信息时输出发起者的语音。