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    APPARATUS AND METHOD FOR SIMULATING A RECONFIGURABLE PROCESSOR
    2.
    发明申请
    APPARATUS AND METHOD FOR SIMULATING A RECONFIGURABLE PROCESSOR 有权
    用于模拟可重构加工器的装置和方法

    公开(公告)号：US20110246170A1

    公开(公告)日：2011-10-06

    申请号：US13012945

    申请日：2011-01-25

    申请人： Tae-Wook Oh ,  Soo-Jung Ryu ,  Yoon-Jin Kim ,  Woong Seo ,  Young-Chul Cho ,  II-Hyun Park

    发明人： Tae-Wook Oh ,  Soo-Jung Ryu ,  Yoon-Jin Kim ,  Woong Seo ,  Young-Chul Cho ,  II-Hyun Park

    IPC分类号： G06F9/45

    CPC分类号： G06F17/5054 ,  G06F17/5022 ,  G06F17/5077

    摘要： A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file.

    摘要翻译： 提供了一种用于评估执行应用程序的处理器性能的处理器模拟技术。 处理器模拟技术可以用于优化应用程序的执行。 包括多个功能单元的可重配置处理器的模拟器包括通过在生成操作数的功能单元和消耗操作数的功能单元之间表示路由路径来建模处理器。 可以根据从调度器接收到的模调度，基于关于功能单元之间的路由延迟和迭代循环的阶段信息的信息来确定每个队列的大小。 还提供了存储用于路由队列操作的面向主机的二进制代码的建模代码DB。 可以通过执行与二进制文件相对应的主机定向二进制代码而不是二进制文件来执行模拟。

    Apparatus to access multi-bank memory
    3.
    发明授权
    Apparatus to access multi-bank memory 有权
    用于访问多行存储器的设备

    公开(公告)号：US09086959B2

    公开(公告)日：2015-07-21

    申请号：US12902681

    申请日：2010-10-12

    申请人： Woong Seo ,  Soo-Jung Ryu ,  Yoon-Jin Kim ,  Young-Chul Cho ,  Il-Hyun Park ,  Tae-Wook Oh

    发明人： Woong Seo ,  Soo-Jung Ryu ,  Yoon-Jin Kim ,  Young-Chul Cho ,  Il-Hyun Park ,  Tae-Wook Oh

    IPC分类号： G06F12/10 ,  G06F12/06 ,  G06F3/06 ,  G06F12/02

    CPC分类号： G06F12/0607 ,  G06F3/067 ,  G06F12/0215 ,  G06F12/0292

    摘要： A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made.

    摘要翻译： 提供一种控制对多存储体存储器的访问的方法以及执行该方法的装置。 对于访问控制，提供步幅寄存器以在运行时间期间存储由处理器确定的步幅值。 存储器控制器以交错方式控制行和列方向上的逻辑块的访问，该逻辑块具有根据存储在步幅寄存器中的步幅值确定的宽度。 因此，可以在行和列方向相邻的连续地址处同时访问多条数据。

    APPARATUS TO ACCESS MULTI-BANK MEMORY
    5.
    发明申请
    APPARATUS TO ACCESS MULTI-BANK MEMORY 有权
    用于访问多银行存储器的设备

    公开(公告)号：US20110087821A1

    公开(公告)日：2011-04-14

    申请号：US12902681

    申请日：2010-10-12

    申请人： Woong SEO ,  Soo-Jung Ryu ,  Yoon-Jin Kim ,  Young-Chul Cho ,  Il-Hyun Park ,  Tae-Wook Oh

    发明人： Woong SEO ,  Soo-Jung Ryu ,  Yoon-Jin Kim ,  Young-Chul Cho ,  Il-Hyun Park ,  Tae-Wook Oh

    IPC分类号： G06F12/10

    CPC分类号： G06F12/0607 ,  G06F3/067 ,  G06F12/0215 ,  G06F12/0292

    摘要： A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made.

    摘要翻译： 提供一种控制对多存储体存储器的访问的方法以及执行该方法的装置。 对于访问控制，提供步幅寄存器以在运行时间期间存储由处理器确定的步幅值。 存储器控制器以交错方式控制行和列方向上的逻辑块的访问，该逻辑块具有根据存储在步幅寄存器中的步幅值确定的宽度。 因此，可以在行和列方向相邻的连续地址处同时访问多条数据。

    Apparatus and method for simulating a reconfigurable processor
    7.
    发明授权
    Apparatus and method for simulating a reconfigurable processor 有权
    用于模拟可重构处理器的装置和方法

    公开(公告)号：US08725486B2

    公开(公告)日：2014-05-13

    申请号：US13012945

    申请日：2011-01-25

    申请人： Tae-Wook Oh ,  Soo-Jung Ryu ,  Yoon-Jin Kim ,  Woong Seo ,  Young-Chul Cho ,  Il-Hyun Park

    发明人： Tae-Wook Oh ,  Soo-Jung Ryu ,  Yoon-Jin Kim ,  Woong Seo ,  Young-Chul Cho ,  Il-Hyun Park

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5022 ,  G06F17/5077

    摘要： A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file.

    摘要翻译： 提供了一种用于评估执行应用程序的处理器性能的处理器模拟技术。 处理器模拟技术可以用于优化应用程序的执行。 包括多个功能单元的可重构处理器的模拟器通过在生成操作数的功能单元之间表示路由路径以及消耗操作数的功能单元来对处理器进行建模。 可以根据从调度器接收到的模调度，基于关于功能单元之间的路由延迟和迭代循环的阶段信息的信息来确定每个队列的大小。 还提供了存储用于路由队列操作的面向主机的二进制代码的建模代码DB。 可以通过执行与二进制文件相对应的主机定向二进制代码而不是二进制文件来执行模拟。