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    Silicon on insulator device having trench isolation layer and method for manufacturing the same
    2.
    发明授权
    Silicon on insulator device having trench isolation layer and method for manufacturing the same 有权
    具有沟槽隔离层的绝缘体上硅器件及其制造方法

    公开(公告)号：US06737706B2

    公开(公告)日：2004-05-18

    申请号：US10114215

    申请日：2002-04-02

    申请人： Tae-jung Lee ,  Byung-sun Kim ,  Myoung-hwan Oh ,  Seung-han Yoo ,  Myung-sun Shin ,  Sang-wook Park

    发明人： Tae-jung Lee ,  Byung-sun Kim ,  Myoung-hwan Oh ,  Seung-han Yoo ,  Myung-sun Shin ,  Sang-wook Park

    IPC分类号： H01L2701

    CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/78615 ,  H01L29/78636

    摘要： A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.

    摘要翻译： 绝缘体上硅（SOI）器件及其制造方法包括：衬底，其包括基底层，掩埋氧化物层和半导体层;以及隔离层，其形成在沟槽中，所述沟槽限定 半导体层上的有源区。 沟槽包括深度小于半导体层的厚度的第一区域和具有与半导体层的厚度一样多的深度的第二区域。 隔离层包括沿着沟槽的表面依次形成的氧化物层和氮化物衬垫以及填充沟槽的电介质层。

    EEPROM having single gate structure
    4.
    发明授权
    EEPROM having single gate structure 有权
    具有单门结构的EEPROM

    公开(公告)号：US07755135B2

    公开(公告)日：2010-07-13

    申请号：US11682619

    申请日：2007-03-06

    申请人： Seung-han Yoo ,  Hoon Chang

    发明人： Seung-han Yoo ,  Hoon Chang

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11558

    摘要： An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap.

    摘要翻译： 电可擦除可编程只读存储器（EEPROM）包括存取晶体管，其具有形成在第一阱中的浮置栅极的相对侧处的浮置栅极和源极/漏极区域，形成在第一阱中的第一阱阱，控制栅极 位于第二区域上，形成在第二区域中的控制栅极的两侧的第一杂质区域和形成在第三区域中的第二阱阱。 为了擦除存储在存储单元中的信息，将预定的擦除电压施加到存取晶体管和第一阱抽头的源极/漏极区域，对第二区域中的第一杂质区域施加接地电压， 大于0V并且小于有源区和第一阱之间的结击穿电压的电压被施加到第二阱分接头。

    EEPROM having single gate structure and method of operating the same
    5.
    发明授权
    EEPROM having single gate structure and method of operating the same 有权
    具有单门结构的EEPROM及其操作方法

    公开(公告)号：US08189399B2

    公开(公告)日：2012-05-29

    申请号：US12787629

    申请日：2010-05-26

    申请人： Seung-han Yoo ,  Hoon Chang

    发明人： Seung-han Yoo ,  Hoon Chang

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11558

    摘要： An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap.

    摘要翻译： 电可擦除可编程只读存储器（EEPROM）包括存取晶体管，其具有形成在第一阱中的浮置栅极的相对侧处的浮置栅极和源极/漏极区域，形成在第一阱中的第一阱阱，控制栅极 位于第二区域上，形成在第二区域中的控制栅极的两侧的第一杂质区域和形成在第三区域中的第二阱阱。 为了擦除存储在存储单元中的信息，将预定的擦除电压施加到存取晶体管和第一阱抽头的源极/漏极区域，对第二区域中的第一杂质区域施加接地电压， 大于0V并且小于有源区和第一阱之间的结击穿电压的电压被施加到第二阱分接头。

    EEPROM Having Single Gate Structure and Method of Operating the Same
    6.
    发明申请
    EEPROM Having Single Gate Structure and Method of Operating the Same 有权
    具有单门结构的EEPROM及其操作方法

    公开(公告)号：US20100238738A1

    公开(公告)日：2010-09-23

    申请号：US12787629

    申请日：2010-05-26

    申请人： Seung-han Yoo ,  Hoon Chang

    发明人： Seung-han Yoo ,  Hoon Chang

    IPC分类号： G11C16/04

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11558

    摘要： An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap.

    摘要翻译： 电可擦除可编程只读存储器（EEPROM）包括存取晶体管，其具有形成在第一阱中的浮置栅极的相对侧处的浮置栅极和源极/漏极区域，形成在第一阱中的第一阱阱，控制栅极 位于第二区域上，形成在第二区域中的控制栅极的两侧的第一杂质区域和形成在第三区域中的第二阱阱。 为了擦除存储在存储单元中的信息，将预定的擦除电压施加到存取晶体管和第一阱抽头的源极/漏极区域，对第二区域中的第一杂质区域施加接地电压， 大于0V并且小于有源区和第一阱之间的结击穿电压的电压被施加到第二阱分接头。