公开(公告)号：US06737706B2

公开(公告)日：2004-05-18

申请号：US10114215

申请日：2002-04-02

申请人： Tae-jung Lee ,  Byung-sun Kim ,  Myoung-hwan Oh ,  Seung-han Yoo ,  Myung-sun Shin ,  Sang-wook Park

发明人： Tae-jung Lee ,  Byung-sun Kim ,  Myoung-hwan Oh ,  Seung-han Yoo ,  Myung-sun Shin ,  Sang-wook Park

IPC分类号： H01L2701

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/78615 ,  H01L29/78636

摘要： A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.

摘要翻译： 绝缘体上硅（SOI）器件及其制造方法包括：衬底，其包括基底层，掩埋氧化物层和半导体层;以及隔离层，其形成在沟槽中，所述沟槽限定 半导体层上的有源区。 沟槽包括深度小于半导体层的厚度的第一区域和具有与半导体层的厚度一样多的深度的第二区域。 隔离层包括沿着沟槽的表面依次形成的氧化物层和氮化物衬垫以及填充沟槽的电介质层。

公开(公告)号：US06995447B2

公开(公告)日：2006-02-07

申请号：US10810285

申请日：2004-03-26

申请人： Tae-jung Lee ,  Byung-sun Kim ,  Myoung-hwan Oh ,  Seung-han Yoo ,  Myung-sun Shin ,  Sang-wook Park

发明人： Tae-jung Lee ,  Byung-sun Kim ,  Myoung-hwan Oh ,  Seung-han Yoo ,  Myung-sun Shin ,  Sang-wook Park

IPC分类号： H10L29/00 ,  H10L27/01 ,  H10L29/76 ,  H10L29/40

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/78615 ,  H01L29/78636

摘要： A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.

公开(公告)号：US07348241B2

公开(公告)日：2008-03-25

申请号：US11384727

申请日：2006-03-20

申请人： Joon-hyung Lee ,  Byung-sun Kim ,  Tae-jung Lee

发明人： Joon-hyung Lee ,  Byung-sun Kim ,  Tae-jung Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7881

摘要： Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack. Thus, ultraviolet rays can penetrate through the window and easily erase charges of the programmed cell.

摘要翻译： 提供EPROM器件的单元结构及其制造方法。 电池结构包括栅极堆叠，其包括第一浮置栅极，包括氮化物层的绝缘图案和顺序地堆叠在半导体衬底上的控制栅极，并且包括用于暴露所述顶部表面或两个侧壁的窗口 第一个浮动栅极位于控制栅极的两侧，使得第一个浮动栅极的电荷可以被紫外线消除。 电池结构还包括浮栅晶体管，其包括形成在半导体衬底上的栅极绝缘层，形成在栅极绝缘层上并连接到栅堆叠中的第一浮栅的第二浮栅，以及源极 /漏极，其形成在半导体衬底中以便与第二浮栅对准。 在电池结构中，窗口形成在栅堆叠的第一浮栅的顶表面或两个侧壁上。 因此，紫外线可以穿过窗口并容易地擦除编程单元的电荷。

公开(公告)号：US07053443B2

公开(公告)日：2006-05-30

申请号：US10702350

申请日：2003-11-06

申请人： Joon-hyung Lee ,  Byung-sun Kim ,  Tae-jung Lee

发明人： Joon-hyung Lee ,  Byung-sun Kim ,  Tae-jung Lee

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7881

摘要： Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack. Thus, ultraviolet rays can penetrate through the window and easily erase charges of the programmed cell.

公开(公告)号：US20060160293A1

公开(公告)日：2006-07-20

申请号：US11384727

申请日：2006-03-20

申请人： Joon-hyung Lee ,  Byung-sun Kim ,  Tae-jung Lee

发明人： Joon-hyung Lee ,  Byung-sun Kim ,  Tae-jung Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7881

摘要： Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack. Thus, ultraviolet rays can penetrate through the window and easily erase charges of the programmed cell.

摘要翻译： 提供EPROM器件的单元结构及其制造方法。 电池结构包括栅极堆叠，其包括第一浮置栅极，包括氮化物层的绝缘图案和顺序地堆叠在半导体衬底上的控制栅极，并且包括用于暴露所述顶部表面或两个侧壁的窗口 第一个浮动栅极位于控制栅极的两侧，使得第一个浮动栅极的电荷可以被紫外线消除。 电池结构还包括浮栅晶体管，其包括形成在半导体衬底上的栅极绝缘层，形成在栅极绝缘层上并连接到栅堆叠中的第一浮栅的第二浮栅，以及源极 /漏极，其形成在半导体衬底中以便与第二浮栅对准。 在电池结构中，窗口形成在栅堆叠的第一浮栅的顶表面或两个侧壁上。 因此，紫外线可以穿过窗口并容易地擦除编程单元的电荷。

公开(公告)号：US08143690B2

公开(公告)日：2012-03-27

申请号：US12219336

申请日：2008-07-21

申请人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

发明人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

IPC分类号： H01L27/06

CPC分类号： H01L27/0814 ,  H01L27/0255

摘要： Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

摘要翻译： 提供具有片上型静电放电（ESD）保护电路的半导体器件及其制造方法。 片上型ESD保护电路可以包括具有与半导体衬底中的第二导电类型区域接触的第一导电类型区域的第一结二极管和具有布置在第一导电类型区域上并与第一导电类型区域接触的金属材料层的第一肖特基二极管 的半导体衬底。

公开(公告)号：US06885609B2

公开(公告)日：2005-04-26

申请号：US10724687

申请日：2003-12-02

申请人： Tae-jung Lee ,  Byung-sun Kim ,  Joon-hyung Lee

发明人： Tae-jung Lee ,  Byung-sun Kim ,  Joon-hyung Lee

IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C8/00 ,  G11C11/00

CPC分类号： G11C8/16

摘要： A layout of a memory cell of a dual-port semiconductor memory device provides for one memory cell that includes a total of eight transistors, including two NMOS scan transistors. Among the transistors, two PMOS transistors and six NMOS transistors are disposed in one N-well area and one contiguous P-well area of a semiconductor substrate, respectively. The N-well area is disposed at a corner of the memory cell for improving efficiency of the layout. Since one N-well area and one P-well area are formed in the semiconductor substrate, the size of an isolated area between the N-well area and the P-well area can be reduced, thus also reducing the size of a memory cell.

摘要翻译： 双端口半导体存储器件的存储单元的布局提供了一个存储单元，其包括总共八个晶体管，包括两个NMOS扫描晶体管。 在晶体管中，两个PMOS晶体管和六个NMOS晶体管分别设置在半导体衬底的一个N阱区域和一个邻接的P阱区域中。 N阱区域设置在存储单元的拐角处，以提高布局的效率。 由于在半导体衬底中形成一个N阱区和一个P阱区，所以可以减小N阱区和P阱区之间的隔离区的大小，从而也减小了存储单元的尺寸 。

公开(公告)号：US20090020844A1

公开(公告)日：2009-01-22

申请号：US12219336

申请日：2008-07-21

申请人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

发明人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

IPC分类号： H01L27/06

CPC分类号： H01L27/0814 ,  H01L27/0255

摘要： Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

摘要翻译： 提供具有片上型静电放电（ESD）保护电路的半导体器件及其制造方法。 片上型ESD保护电路可以包括具有与半导体衬底中的第二导电类型区域接触的第一导电类型区域的第一结二极管和具有布置在第一导电类型区域上并与第一导电类型区域接触的金属材料层的第一肖特基二极管 的半导体衬底。

公开(公告)号：US07671406B2

公开(公告)日：2010-03-02

申请号：US11834129

申请日：2007-08-06

申请人： Sang-soo Kim ,  Byung-sun Kim

发明人： Sang-soo Kim ,  Byung-sun Kim

IPC分类号： H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A method of fabricating a semiconductor device having a non-volatile memory cell includes forming an insulation layer as an uppermost/outermost portion of the memory cell to enhance the charge retention capability of the memory cell. The insulation layer is formed after the gate structure and integrate dielectric of the non-volatile memory cell, and a gate of a logic transistor are formed. The insulation layer thus enhances the function of the intergate dielectric. Subsequently, a conductive layer is formed on the substrate including over the gate of the logic transistor. A silicide layer is then formed on the gate of the logic transistor and on the substrate adjacent opposite sides of the gate. The insulation layer thus also serves prevent the formation of a silicide layer on the non-volatile memory cell.

摘要翻译： 制造具有非易失性存储单元的半导体器件的方法包括形成作为存储单元的最上/最外部分的绝缘层，以增强存储单元的电荷保持能力。 在栅极结构之后形成绝缘层并且整合非易失性存储单元的电介质，并且形成逻辑晶体管的栅极。 因此，绝缘层增强了隔间电介质的功能。 随后，在包括在逻辑晶体管的栅极上的衬底上形成导电层。 然后在逻辑晶体管的栅极上和邻近栅极的相对侧的衬底上形成硅化物层。 因此，绝缘层也用于防止在非易失性存储单元上形成硅化物层。

公开(公告)号：US09516086B2

公开(公告)日：2016-12-06

申请号：US14238664

申请日：2012-08-13

申请人： Hong-seok Park ,  Byung-sun Kim ,  Sang-jin Hahm ,  Jin-mo Kang ,  Keun-sik Lee ,  Jae-jun Lee ,  Yong-seok Jang ,  Hee-jean Kim ,  Dae-jong Lee ,  Yu-sung Joo

发明人： Hong-seok Park ,  Byung-sun Kim ,  Sang-jin Hahm ,  Jin-mo Kang ,  Keun-sik Lee ,  Jae-jun Lee ,  Yong-seok Jang ,  Hee-jean Kim ,  Dae-jong Lee ,  Yu-sung Joo

IPC分类号： H04L29/06 ,  H04N21/2389 ,  H04N21/63 ,  H04N21/845 ,  H04N21/8547

CPC分类号： H04L65/607 ,  H04L65/4076 ,  H04N21/2389 ,  H04N21/631 ,  H04N21/8456 ,  H04N21/8547

摘要： A transmitting device which transmits a plurality of streams is provided. The transmitting device comprises: a first multimedia data consisting of multimedia contents; a first synchronization information for synchronization of a second multimedia data consisting of multimedia contents; a first transmitting data including a first signaling data for the first multimedia data and a second signaling data for the second multimedia data, a data generating unit generating a second transmitting data including a second synchronization information for synchronization of the second multimedia data and the first multimedia data, a first transmitting unit transmitting the first transmitting data supplied from the data generating unit to a receiving device through a broadcasting network, and a second transmitting unit transmitting the second transmitting data supplied from the data generating unit to the receiving device through an IP network.

摘要翻译： 提供了发送多个流的发送装置。 发送装置包括：由多媒体内容组成的第一多媒体数据; 用于同步由多媒体内容组成的第二多媒体数据的第一同步信息; 第一发送数据，包括第一多媒体数据的第一信令数据和第二多媒体数据的第二信令数据;数据生成单元，生成包括用于第二多媒体数据和第一多媒体数据的同步的第二同步信息的第二发送数据 数据，第一发送单元，通过广播网络将从数据生成单元提供的第一发送数据发送到接收装置;以及第二发送单元，其通过IP网络将从数据生成单元提供的第二发送数据发送到接收装置 。