公开(公告)号：US08745559B2

公开(公告)日：2014-06-03

申请号：US13872180

申请日：2013-04-29

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chih-Cheng Chou ,  Ke-Ying Su

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/40

Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings.

Abstract translation: 一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括至少一个管芯，所述至少一个管芯包括要使用单个图案化工艺或多图案化工艺中的至少一个形成的至少一个金属层，创建包括近似于 基于技术文件，在至少一个管芯的金属层中的导体之间的电容或电感耦合中的至少一个，模拟基于网表的集成电路的性能，基于网络调整至少一个管芯和插入器之间的布线，基于 模拟以减少电容或电感耦合中的至少一个，并且重复模拟和调整以优化电容或电感耦合中的至少一个。