公开(公告)号：US20230009031A1

公开(公告)日：2023-01-12

申请号：US17648836

申请日：2022-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui Fu Hsieh ,  Chia-Chi Yu ,  Chih-Teng Liao ,  Yi-Jen Chen ,  Chia-Cheng Tai

IPC: H01L21/66 ,  H01L21/311

Abstract: A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.

公开(公告)号：US11430893B2

公开(公告)日：2022-08-30

申请号：US16926521

申请日：2020-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yan-Ting Shen ,  Chia-Chi Yu ,  Chih-Teng Liao ,  Yu-Li Lin ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

公开(公告)号：US20240379470A1

公开(公告)日：2024-11-14

申请号：US18782419

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui Fu Hsieh ,  Chia-Chi Yu ,  Chih-Teng Liao ,  Yi-Jen Chen ,  Chia-Cheng Tai

IPC: H01L21/66 ,  H01L21/311

Abstract: A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.

公开(公告)号：US11282944B2

公开(公告)日：2022-03-22

申请号：US16945557

申请日：2020-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Chi Yu ,  Jui Fu Hseih ,  Yu-Li Lin ,  Chih-Teng Liao ,  Yi-Jen Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311 ,  H01L29/08 ,  H01L29/06

Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

公开(公告)号：US12165936B2

公开(公告)日：2024-12-10

申请号：US17648836

申请日：2022-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui Fu Hsieh ,  Chia-Chi Yu ,  Chih-Teng Liao ,  Yi-Jen Chen ,  Chia-Cheng Tai

IPC: H01L21/66 ,  H01L21/311

Abstract: A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.