公开(公告)号：US20240371818A1

公开(公告)日：2024-11-07

申请号：US18310293

申请日：2023-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Chun Yang ,  Jui Hsuan Tsai ,  Chiao-Chun Chang ,  Chu-Chuan Huang ,  Jih-Churng Twu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/538

Abstract: A process includes depositing an edge fill dielectric over a first workpiece and a device disposed thereon. The edge fill dielectric is patterned so that only the edge portions remain. A second dielectric material is formed over the first workpiece, device, and edge fill dielectric. A planarization process levels the second dielectric material and the device. A bonding layer is formed thereon and a second workpiece bonded thereto by a dielectric-to-dielectric bond.