公开(公告)号：US20240371818A1

公开(公告)日：2024-11-07

申请号：US18310293

申请日：2023-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Chun Yang ,  Jui Hsuan Tsai ,  Chiao-Chun Chang ,  Chu-Chuan Huang ,  Jih-Churng Twu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/538

Abstract: A process includes depositing an edge fill dielectric over a first workpiece and a device disposed thereon. The edge fill dielectric is patterned so that only the edge portions remain. A second dielectric material is formed over the first workpiece, device, and edge fill dielectric. A planarization process levels the second dielectric material and the device. A bonding layer is formed thereon and a second workpiece bonded thereto by a dielectric-to-dielectric bond.

公开(公告)号：US11443981B2

公开(公告)日：2022-09-13

申请号：US16866565

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Li Hsiao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang

IPC: H01L21/768 ,  H01L21/50 ,  H01L21/60

Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.

公开(公告)号：US09893046B2

公开(公告)日：2018-02-13

申请号：US15205238

申请日：2016-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Chun Yang ,  Yi-Li Hsiao ,  Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/30604 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/18161

Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.

公开(公告)号：US20250031434A1

公开(公告)日：2025-01-23

申请号：US18353389

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Jih-Churng Twu ,  Su-Chun Yang ,  Shih-Peng Tai ,  Yu-Hao Kuo

IPC: H01L21/822 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.

公开(公告)号：US11456256B2

公开(公告)日：2022-09-27

申请号：US16885282

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang ,  Wen-Lin Shih

IPC: H01L23/538 ,  H01L23/373 ,  H01L25/065 ,  H01L21/768 ,  H01L21/50

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

公开(公告)号：US20210375766A1

公开(公告)日：2021-12-02

申请号：US16885282

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang ,  Wen-Lin Shih

IPC: H01L23/538 ,  H01L23/373 ,  H01L25/065 ,  H01L21/50 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

公开(公告)号：US11101195B2

公开(公告)日：2021-08-24

申请号：US16373915

申请日：2019-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Liang Shao ,  Wen-Lin Shih ,  Su-Chun Yang ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00

Abstract: A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.

公开(公告)号：US20250053064A1

公开(公告)日：2025-02-13

申请号：US18448337

申请日：2023-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Chun Yang ,  Chen Chiang Yu ,  Jui Hsuan Tsai ,  Jih-Churng Twu ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: G02F1/355 ,  G02F1/35

Abstract: Optical devices and methods of manufacture are presented in which a non-linear material is deposited or otherwise placed. Once the non-linear material has been deposited, implantation regions are formed within the non-linear material using an implantation process. The implantation regions are removed using an etching process, and electrodes are formed to the remaining material.

公开(公告)号：US20220285310A1

公开(公告)日：2022-09-08

申请号：US17664484

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Ying-Jui Huang ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Ching-Hua Hsieh ,  Chien Ling Hwang ,  Yi-Li Hsiao ,  Su-Chun Yang

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

公开(公告)号：US11056459B2

公开(公告)日：2021-07-06

申请号：US16373900

申请日：2019-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hang Tung ,  Tung-Liang Shao ,  Su-Chun Yang ,  Geng-Ming Chang ,  Chen-Hua Yu

IPC: H01L23/00

Abstract: A method for forming a chip package structure is provided. The method includes partially removing a first redistribution layer to form an alignment trench in the first redistribution layer. The alignment trench surrounds a bonding portion of the first redistribution layer. The method includes forming a liquid layer over the bonding portion. The method includes disposing a chip structure over the liquid layer, wherein a first width of the bonding portion is substantially equal to a second width of the chip structure. The method includes evaporating the liquid layer. The chip structure is in direct contact with the bonding portion after the liquid layer is evaporated.