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公开(公告)号：US20240371818A1
公开(公告)日：2024-11-07
申请号：US18310293
申请日：2023-05-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Su-Chun Yang , Jui Hsuan Tsai , Chiao-Chun Chang , Chu-Chuan Huang , Jih-Churng Twu , Chung-Shi Liu
IPC: H01L23/00 , H01L23/538
Abstract: A process includes depositing an edge fill dielectric over a first workpiece and a device disposed thereon. The edge fill dielectric is patterned so that only the edge portions remain. A second dielectric material is formed over the first workpiece, device, and edge fill dielectric. A planarization process levels the second dielectric material and the device. A bonding layer is formed thereon and a second workpiece bonded thereto by a dielectric-to-dielectric bond.
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公开(公告)号：US20250031434A1
公开(公告)日：2025-01-23
申请号：US18353389
申请日：2023-07-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hung Lin , Jih-Churng Twu , Su-Chun Yang , Shih-Peng Tai , Yu-Hao Kuo
IPC: H01L21/822 , H01L21/3065 , H01L21/311 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065
Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.
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公开(公告)号：US11056365B2
公开(公告)日：2021-07-06
申请号：US15800586
申请日：2017-11-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hom-Chung Lin , Jih-Churng Twu , Chin-Yun Chen , Tai-Hsiang Lin , Yu-Chi Tsai
Abstract: A method for fault detection in a fabrication tool is provided. The method includes processing a semiconductor wafer in a fabrication tool according to a plurality of process events of a process run. The method further includes measuring humidity in the fabrication tool in at least one of the process events. The method also includes comparing the humidity measured in one of the process events with an expected humidity associated with the process event. In addition, the method includes based on the comparison, indicating an alarm condition when a difference between the measured humidity and the expected humidity exceeds a range of acceptable values associated with the process event.
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公开(公告)号：US11804392B2
公开(公告)日：2023-10-31
申请号：US17568611
申请日：2022-01-04
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hom-Chung Lin , Chi-Ying Chang , Jih-Churng Twu , Chin-Yun Chen , Yi-Ting Chang , Feng-Yu Chen
IPC: H01L21/67 , H01L21/677
CPC classification number: H01L21/67259 , H01L21/67763
Abstract: A method includes transferring a tool monitoring device to a load port of a tool. An environmental parameter of the load port is monitored by the tool monitoring device. The tool monitoring device is removed from the load port after the environmental parameter of the load port is monitored. A door of the tool in front of the load port is closed. The door of the tool is kept closed during a period from a time of transferring the tool monitoring device to the load port to a time of removing the tool monitoring device from the load port.
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Patent Agency Ranking
公开(公告)号：US11239099B2
公开(公告)日：2022-02-01
申请号：US16539708
申请日：2019-08-13
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hom-Chung Lin , Chi-Ying Chang , Jih-Churng Twu , Chin-Yun Chen , Yi-Ting Chang , Feng-Yu Chen
IPC: H01L21/67 , H01L21/677
Abstract: In some embodiments, a system for monitoring a tool is provided. The system includes a tool monitoring device, a transporting system and an external apparatus. The tool monitoring device is configured to monitor an environmental parameter of a load port of a tool. The tool monitoring device includes a wafer pod and a monitoring module disposed in the wafer pod. The monitoring module includes at least one sensor, a computer coupled to the at least one sensor, a power supply electrically coupled to the at least one sensor and the computer, and a wireless unit coupled to the computer. The transporting system is configured to transfer the tool monitoring device from one load port to another load port. The external apparatus is coupled to the tool monitoring device.
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公开(公告)号：US10741426B2
公开(公告)日：2020-08-11
申请号：US15906152
申请日：2018-02-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jian-Lun Lo , Jih-Churng Twu , Feng-Yu Chen , Yuan-Hsiao Su , Yi-Chi Huang , Yueh-Ting Yang , Shu-Han Chao
Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. In the first thermal mode, a first end thermal zone, a middle thermal zone and a second end thermal zone of the furnace which are arranged in sequence have a gradually increasing temperature. The method also includes controlling the temperature of the furnace in a second thermal mode after the formation of the thin film. In the second thermal mode, the first end thermal zone, the middle thermal zone and the second end thermal zone of the furnace have a gradually decreasing temperature.
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公开(公告)号：US20250053064A1
公开(公告)日：2025-02-13
申请号：US18448337
申请日：2023-08-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Su-Chun Yang , Chen Chiang Yu , Jui Hsuan Tsai , Jih-Churng Twu , Chung-Shi Liu , Chen-Hua Yu
Abstract: Optical devices and methods of manufacture are presented in which a non-linear material is deposited or otherwise placed. Once the non-linear material has been deposited, implantation regions are formed within the non-linear material using an implantation process. The implantation regions are removed using an etching process, and electrodes are formed to the remaining material.
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公开(公告)号：US11569062B2
公开(公告)日：2023-01-31
申请号：US16882053
申请日：2020-05-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hom-Chung Lin , Jih-Churng Twu , Yi-Ting Chang , Chao-Po Lu , Tsung-Min Lin
IPC: H01J37/31 , H01J37/317 , H01J37/08 , H01J37/32
Abstract: An ion implantation system includes an ion implanter containing an ion source unit and a dopant source gas supply system. The system includes a dopant source gas storage tank inside a gas box container located remotely to the ion implanter and a dopant source gas supply pipe configured to supply a dopant source gas from the dopant source gas storage tank to the ion source unit. The dopant source gas supply pipe includes an inner pipe, an outer pipe enclosing the inner pipe, a first pipe adaptor coupled to first end of respective inner and outer pipes, and a second pipe adaptor coupled to seconds end of respective inner and outer pipes opposite the first end. The first pipe adaptor connects the inner pipe to the dopant source gas storage tank and the second pipe adaptor connects the inner pipe to the ion source unit.
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公开(公告)号：US10930527B2
公开(公告)日：2021-02-23
申请号：US16899803
申请日：2020-06-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jian-Lun Lo , Jih-Churng Twu , Feng-Yu Chen , Yuan-Hsiao Su , Yi-Chi Huang , Yueh-Ting Yang , Shu-Han Chao
Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.
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