公开(公告)号：US10819316B2

公开(公告)日：2020-10-27

申请号：US16457459

申请日：2019-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC: H03K3/013 ,  H03K3/023

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

公开(公告)号：US12047075B2

公开(公告)日：2024-07-23

申请号：US17837960

申请日：2022-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC: H03K3/013 ,  H03K3/023

CPC classification number: H03K3/013 ,  H03K3/023

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

公开(公告)号：US10979065B1

公开(公告)日：2021-04-13

申请号：US16836923

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC: H03M1/46

Abstract: A signal processing circuit including a plurality of analog-to-digital conversion circuits, an in-memory computing device, and a control method thereof are provided. Each analog-to-digital conversion circuit includes a reset switch, a capacitor array circuit, a voltage comparator, and a successive approximation circuit. A first terminal of the reset switch receives a first reference voltage, and a second terminal of the reset switch receives an input voltage signal. The capacitor array circuit adjusts the input voltage signal according to a successive approximation control signal to generate an adjusted voltage. The voltage comparator compares the voltage levels of the adjusted voltage and a second reference voltage to generate a comparison signal. The successive approximation circuit generates a successive approximation control signal according to the comparison signal and generates an output digital signal corresponding to the input voltage signal. The capacitor array circuit maintains the input voltage signal during a non-reset stage.

公开(公告)号：US10692549B1

公开(公告)日：2020-06-23

申请号：US16572604

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chow Peng ,  Chin-Ho Chang ,  Jaw-Juinn Horng

IPC: H03M1/12 ,  G11C7/12 ,  G06F12/06 ,  H03M1/06 ,  H03M1/10 ,  H03M1/80 ,  G11C13/00

Abstract: A memory array structure that includes memory columns having first bit lines and second bit lines is introduced. Each of the memory columns includes a bit line pair, a pre-charge switch pair and a first switch pair. Output voltages from the first bit lines and the second bit lines are used to generated a first average voltage and a second average voltage, respectively. One of the first average voltage and the second average voltage is a lower average voltage and another one of the first average voltage and the second average voltage is a higher average voltage. The pre-charge switch pair and the first switch pair of a selected memory column among the plurality of memory columns are controlled to repeatedly perform an incremental step to increment the lower average voltage by a step voltage until the lower average voltage is greater than the higher average voltage.

公开(公告)号：US20200106422A1

公开(公告)日：2020-04-02

申请号：US16457459

申请日：2019-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC: H03K3/013 ,  H03K3/023

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.