公开(公告)号：US11208714B2

公开(公告)日：2021-12-28

申请号：US16181489

申请日：2018-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Chang

IPC: C23C8/80 ,  C23C8/10

Abstract: An apparatus for in situ steam generation oxidation are provided. The apparatus includes a reactor chamber. The apparatus also includes a radiant source over the chamber. The radiant source includes a plurality of lamps for heating the reactor chamber. The apparatus further includes a lamphead over the radiant source for adjusting the temperature of the radiant source. In addition, the apparatus includes a gas inlet system coupled to the lamphead. The gas inlet system includes a mass flow controller for adjusting the flow rate of cooling gas into the lamphead. The apparatus includes a gas outlet system, on the opposite side of the cooling gas inlet system, coupled to the lamphead. The gas outlet system includes a pressure controller for accelerating the exhaust rate of the cooling gas.

公开(公告)号：US11069401B2

公开(公告)日：2021-07-20

申请号：US16895069

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuhsiang Chen ,  Shao-Yu Chou ,  Chun-Hao Chang ,  Min-Shin Wu ,  Yu-Der Chih

IPC: G11C11/41 ,  G11C11/419 ,  G11C11/418 ,  G11C11/409 ,  G11C11/413 ,  G11C7/10

Abstract: Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.

公开(公告)号：US10269420B2

公开(公告)日：2019-04-23

申请号：US15619084

申请日：2017-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuhsiang Chen ,  Shao-Yu Chou ,  Chun-Hao Chang ,  Min-Shin Wu ,  Yu-Der Chih

IPC: G11C11/41 ,  G11C11/419 ,  G11C11/418 ,  G11C11/409 ,  G11C11/413 ,  G11C7/10

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes a first decoder coupled to the first memory array, a second decoder coupled to the second memory array, and an output buffer. The first decoder obtains first data from the first memory array according a first address signal. The second decoder obtains second data from the second memory array according the first address signal. The output buffer selectively provides the first data or the second data as an output according to a control signal. The first data is complementary to the second data.

公开(公告)号：US10706918B2

公开(公告)日：2020-07-07

申请号：US16390517

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuhsiang Chen ,  Shao-Yu Chou ,  Chun-Hao Chang ,  Min-Shin Wu ,  Yu-Der Chih

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/418 ,  G11C11/409 ,  G11C11/413 ,  G11C7/10

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.