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公开(公告)号：US20210175707A1
公开(公告)日：2021-06-10
申请号：US17180345
申请日：2021-02-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hung Chen , Kuo-Ji Chen , Shao-Yu Chou
IPC: H02H9/04 , H01L27/02 , H03K17/082
Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.
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公开(公告)号：US10706918B2
公开(公告)日：2020-07-07
申请号：US16390517
申请日：2019-04-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yuhsiang Chen , Shao-Yu Chou , Chun-Hao Chang , Min-Shin Wu , Yu-Der Chih
IPC: G11C11/40 , G11C11/419 , G11C11/418 , G11C11/409 , G11C11/413 , G11C7/10
Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.
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公开(公告)号：US10163783B1
公开(公告)日：2018-12-25
申请号：US15922439
申请日：2018-03-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Meng-Sheng Chang , Shao-Tung Peng , Shao-Yu Chou , Liang Chuan Chang , Yao-Jen Yang
IPC: G11C17/18 , H01L23/525 , G11C17/16 , H01H85/046 , H01H85/05 , H01L23/50
Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.
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公开(公告)号：US09064799B2
公开(公告)日：2015-06-23
申请号：US14079671
申请日：2013-11-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Hung-Jen Liao , Li-Chun Tien
IPC: H01L21/8238 , H01L21/28 , H01L21/8234 , H01L27/02 , H01L29/78 , H01L29/66
CPC classification number: H01L21/28008 , H01L21/28123 , H01L21/823425 , H01L21/823481 , H01L27/0207 , H01L29/66628 , H01L29/7848
Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.
Abstract translation: 一种方法包括在半导体衬底的有效区域上形成第一多个指状物。 第一多个指状物中的每一个具有在与有源区域的宽度方向平行的方向上延伸的相应长度。 第一多个指状物形成至少一个晶体管的至少一个栅极，该晶体管具有由有源区域的一部分形成的源极和漏极。 第一虚设多晶硅结构形成在第一多个指状物的外部之一和半导体衬底的第一边缘之间的有源区域的一部分上。 第二虚设多晶硅结构在第一虚设多晶硅结构和半导体衬底的第一边缘之间的半导体衬底之上。
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公开(公告)号：US09048655B2
公开(公告)日：2015-06-02
申请号：US13675547
申请日：2012-11-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Qingchao Meng , Lei Pan , Shao-Yu Chou
Abstract: Some embodiments relate to an IC that includes an ESD-susceptible circuit. The IC includes a number of IC pads that are electrically coupled to respective nodes on the ESD-susceptible circuit. The IC pads are electrically accessible from external to the IC, and include one or more power supply pads and one or more I/O pads. The IC also includes a number of ESD protection devices coupled to the plurality of IC pads, respectively. A trigger circuit on the IC is configured to detect an ESD event impingent on a power supply pad and, in response to the detection, to trigger concurrent shunting of energy of the ESD event over both an ESD clamp element of an I/O pad and an ESD clamp element of the power supply pad. Other embodiments are also disclosed.
Abstract translation: 一些实施例涉及包括ESD敏感电路的IC。 IC包括多个IC焊盘，其电耦合到ESD敏感电路上的相应节点。 IC焊盘可以从IC的外部电可访问，并且包括一个或多个电源焊盘和一个或多个I / O焊盘。 IC还包括分别耦合到多个IC焊盘的多个ESD保护器件。 IC上的触发电路被配置为检测照射在电源焊盘上的ESD事件，并且响应于该检测，触发I / O焊盘的ESD钳位元件上ESD事件的能量并发分流，以及 电源板的ESD钳位元件。 还公开了其他实施例。
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Patent Agency Ranking
公开(公告)号：US20220302699A1
公开(公告)日：2022-09-22
申请号：US17837948
申请日：2022-06-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hung CHEN , Kuo-Ji Chen , Shao-Yu Chou
IPC: H02H9/04 , H03K17/082 , H01L27/02
Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.
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公开(公告)号：US20140118869A1
公开(公告)日：2014-05-01
申请号：US13675547
申请日：2012-11-13
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Qingchao Meng , Lei Pan , Shao-Yu Chou
IPC: H02H9/04
Abstract: Some embodiments relate to an IC that includes an ESD-susceptible circuit. The IC includes a number of IC pads that are electrically coupled to respective nodes on the ESD-susceptible circuit. The IC pads are electrically accessible from external to the IC, and include one or more power supply pads and one or more I/O pads. The IC also includes a number of ESD protection devices coupled to the plurality of IC pads, respectively. A trigger circuit on the IC is configured to detect an ESD event impingent on a power supply pad and, in response to the detection, to trigger concurrent shunting of energy of the ESD event over both an ESD clamp element of an I/O pad and an ESD clamp element of the power supply pad. Other embodiments are also disclosed.
Abstract translation: 一些实施例涉及包括ESD敏感电路的IC。 IC包括多个IC焊盘，其电耦合到ESD敏感电路上的相应节点。 IC焊盘可以从IC的外部电可访问，并且包括一个或多个电源焊盘和一个或多个I / O焊盘。 IC还包括分别耦合到多个IC焊盘的多个ESD保护器件。 IC上的触发电路被配置为检测照射在电源焊盘上的ESD事件，并且响应于该检测，触发I / O焊盘的ESD钳位元件上ESD事件的能量并发分流，以及 电源板的ESD钳位元件。 还公开了其他实施例。
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公开(公告)号：US11670941B2
公开(公告)日：2023-06-06
申请号：US17837948
申请日：2022-06-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hung Chen , Kuo-Ji Chen , Shao-Yu Chou
IPC: H02H9/04 , H03K17/082 , H01L27/02
CPC classification number: H02H9/046 , H01L27/0266 , H01L27/0285 , H03K17/0822
Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.
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公开(公告)号：US11374403B2
公开(公告)日：2022-06-28
申请号：US17180345
申请日：2021-02-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hung Chen , Kuo-Ji Chen , Shao-Yu Chou
IPC: H02H9/04 , H03K17/082 , H01L27/02
Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.
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公开(公告)号：US11069401B2
公开(公告)日：2021-07-20
申请号：US16895069
申请日：2020-06-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yuhsiang Chen , Shao-Yu Chou , Chun-Hao Chang , Min-Shin Wu , Yu-Der Chih
IPC: G11C11/41 , G11C11/419 , G11C11/418 , G11C11/409 , G11C11/413 , G11C7/10
Abstract: Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.
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